EDA Design Page 193

http://www.arm.com。 The ARM® RealView® Development Suite 3.1 Professional is a complete, end-to-end solution for software development supporting all ARM® processors and ARM CoreSight™ debug technology. This full-featured product enables developers to begin software development, optimization and test ahead of silicon availability, significantly reducing application time-to-market and ensuring the highest degree of software quality. RealView® Development Suite 3.1 Professional incorporates the best-in-class RealView Compilation tools and market-leading RealView Profiler enabling applications to easily achieve both high performance and optimal code size. The product includes support for the latest Cortex™-A8 processor and includes vectorizing compilation for the NEON™ media processing engine which can increase the performance of multimedia applications in standard C code by more than 200%. RealView Development Suite 3.1 Professional...

::::::English Description:::::: Code Composer Studio 3.3; (CCStudio) Development Tools are a key element of the eXpressDSP Software and Development Tools strategy from Texas Instruments. CCStudio delivers all of the host tools and runtime software support for your TMS320 DSP based real-time embedded application to market faster. Familiar tools and interfaces allow users to get started faster than ever before and add functionality to their application thanks to sophisticated productivity tools. CCStudio’s easy to use development environment allows DSP designers of all experience levels to move quickly through each phase of the application development process including design, code and build, debug, analyze and optimize. Kit Components The fully integrated development environment includes, real-time analysis capabilities, easy to use debugger, C/C++ Compiler,...

HI-TECH for dsPIC®/PIC24 v9.60PL2 Compiler for Microchips dsPIC Digital Signal Controller (DSC) range HI-TECH for dsPIC/PIC24 compiler offers the C programmer a powerful, yet easy-to-use environment for code development. HI-TECH for dsPIC/PIC24 Compiler Features: ANSI C, full featured and portable, supporting all standard data types (IEEE floating point, long data types, etc…) Reliable – based on mature, field-proven technology used in our PICC and PICC-18 compilers Unlimited number of source files Multiple optimization levels and types Comprehensive C library with all source code provided Mixed C and assembler programming Listings showing generated assembler Optimizing assembler Compatible – integrates into the MPLAB® IDE, MPLAB ICD2 and most 3rd-party development tools Runs on multiple platforms: Windows® (including 32-bit Vista), Linux®, UNIX® Integrated...

::::::English Description:::::: PICC-18 PRO v9.61 ANSI C COMPILER*, based on the reliable PICC-18 STD compiler, comes with: Omniscient Code Generation™ Extracts information from multiple source files simultaneously, allowing more intelligent state-of-the-art code generation that: Automatically handles memory banking without requiring special qualifiers; Optimizes the size of each pointer variable in your code based on its usage; Eliminates the need for many non-standard C qualifiers and compiler options; Produces more optimal interrupt context switching code; and Customizes the functionality of the included printf library function. This all means you can spend less time worrying about device memory requirements and compiler-specific semantics and more time focusing on your goals. * Can run on multiple platforms including Windows (does not include Vista), Linux...

。 ::::::English Description:::::: HI-TECH PICC™ v9.60PL1 is a high-performance C compiler for the Microchip PICmicro® 10/12/14/16/17 series of microcontrollers. HI-TECH PICC STD Compiler Features: ANSI C – full featured and portable Reliable – mature, field-proven technology Multiple C optimization levels An optimizing assembler Full linker, with overlaying of local variables to minimize RAM usage Comprehensive C library with all source code provided Includes support for 24-bit and 32-bit IEEE floating point and 32-bit long data types Mixed C and assembler programming Unlimited number of source files Listings showing generated assembler Compatible – integrates into the MPLAB® IDE, MPLAB ICD2 and most 3rd-party development tools Runs on multiple platforms: Windows (up to Vista64), Linux and Mac OS X HI-TECH PICC STD...

The third product in the process-aware design-for-manufacturing (PA-DFM) family is Fammos; the first special-purpose TCAD PA-DFM tool that analyzes stress evolution for the entire fabrication process of interconnects. Fammos performs 3D backend process simulations using design database and process recipes. With specialized algorithms for fast 3D structure construction, mesh generation, and equation solving, Fammos predicts interconnect stress distributions from multiple stress sources and accounts for proximity effects. Combining the best-in-class capabilities from Synopsys, Fammos is capable of detecting stress hot spots that are susceptible to debonding, voiding and cracking. It employs a set of physics-based models to evaluate reliability failures. Using the Sentaurus Workbench user interface, Fammos will facilitate technology explorations with parameterized input files and scheduled run splits. Benefits...

::::::English Description:::::: HDL Designer Linux delivers solutions optimizing the design creation, synthesis and verification processes of advanced ASIC and FPGA designs in a team environment. Comprehensive Design Creation & RTL Reuse Environment Any Silicon PLD, FPGA, Platform FPGA, Structured ASIC, ASIC Prototypes, ASICs and SOCs Any Vendor Actel, Altera, Atmel, ChipExpress, Lattice, Xilinx, plus any ASIC foundry Any Language VHDL, Verilog, SystemVerilog, C/C++, PSL Any Flow Integrated with all leading Simulation, Emulation & Formal solutions Integrated with all commercial synthesis and P & R environments Optimizing RTL Reuse Practical reuse (online demo) (datasheet) Optimizing The Design Process Cut design time in half: Rapid design development process Team productivity: Team design flow and version management Tune your competitive edge: Flow management...

::::::English Description:::::: HDL Designer delivers solutions optimizing the design creation, synthesis and verification processes of advanced ASIC and FPGA designs in a team environment. Comprehensive Design Creation & RTL Reuse Environment Any Silicon PLD, FPGA, Platform FPGA, Structured ASIC, ASIC Prototypes, ASICs and SOCs Any Vendor Actel, Altera, Atmel, ChipExpress, Lattice, Xilinx, plus any ASIC foundry Any Language VHDL, Verilog, SystemVerilog, C/C++, PSL Any Flow Integrated with all leading Simulation, Emulation & Formal solutions Integrated with all commercial synthesis and P & R environments Optimizing RTL Reuse Practical reuse (online demo) (datasheet) Optimizing The Design Process Cut design time in half: Rapid design development process Team productivity: Team design flow and version management Tune your competitive edge: Flow management and...

* FAST-Quickly visualize your complex HDL Design * Intuitive-Designed by EEs for EEs * Correct-Sunburst Design Rule checking, gets your design correct before simulation * Yours- Don\’t design our way, design it your way. Graphical or Text, it\’s your choice * Fast graphical design visualization * Support for incomplete designs * Popular text editor emulation Vi vs Emacs? How about both? * Automatically place modules correctly in your design * annotate thirdparty tools for easy visualization of the problems * Robust Command Line Interface APIProduct:StelarTools HDLE 2005.1 Lanaguage:english Platform:Winxp/Win7 Size:46MB

　电路板设计解决方案市场和技术领导者Mentor Graphics宣布推出HyperLynx 7.7版，这套强大而易于使用的布局前和布局后讯号完整性仿真与分析工具包含多项生产力和技术增强功能，最适合支持PCI-Express、Hyper Transport、XAUI和SATA/SAS等最新的SERDES联机标准。　这是专门用于Mentor Graphics Vendor-Independent Flow 2006-IND2006的版本。　 　　「 高速数字设计实用手册」(High-Speed Digital Design: A Handbook of Black Magic) 一书作者Howard Johnson博士表示：「HyperLynx 7.7新增加任意线路图编辑器和先进的高速分析功能，不但产品变得更实用，操作也更简单。所有数字设计人员都应该购买、学习和使用这套工具。」　　 　　　新提供的生产力增强功能包括简单易用的「任意形状」(free-form) 传输线路编辑器，设计人员可于布局前利用它尝试各种设计 (what-if) 和发展设计约束条件，进而轻松地建立所需的SPICE和S参数模型。HyperLynx 7.7会将所有讯号损耗来源列入考虑，包括封装寄生参数、连接头和导孔损耗以及电路板的电阻性损耗和介质损耗。HyperLynx 7.7会透过一套易于使用的环境管理这些讯号完整性效应，这使其成为全世界应用最广泛的讯号完整性软件。HyperLynx 7.7版还采用Mentor Graphics独有的「导孔显示」(Via Visualizer) 技术，这对于电路板导孔的深入分析有很大帮助。其它技术增强部份还包括批次仿真、更简单的使用者界面、更多的SERDES眼形罩幕 (eye mask)、更强大的SPICE建模功能以及超过13,000种新增IBIS模型。这些增强功能都兼容于所有主要的电路板布局环境，硬件工程师可以更有效地分析10亿位等级 (multi-gigabit) 串行式电路板联机。　　 　　 　SERDES (SERialization/DE-Serialization) 　　　 SERDES是一种快速窜红的连结技术，它能利用速率高达每秒数千兆位的串行驱动器和接收器将半导体组件和FPGA连接在一起。SERDES讯号是透过差动对传输资料，而非采用传统的宽总线架构，零件之间的资料速率最高达10 Gbps。除了资料产出大幅提升之外，SERDES还能减少电路板绕线面积、电路板厚度以及零件和连接头的接脚数。　　 　　　「对许多工程师和电路布局设计人员而言，印刷电路板的SERDES联机设计与分析是一种全新概念。」Mentor Graphics副总裁暨系统设计部门总经理Henry Potts表示，「新推出的HyperLynx不但简化设计作业，还提供完整的布局前和布局后分析能力，现在将有更多使用者可以利用这种联机技术发展效能更高的系统。」　　 　　　主要FPGA厂商的评论　　　「视讯和影像处理等应用都已采用PCI-Express等高速串行联机技术。」Altera的EDA厂商公关主管James Smith表示，「HyperLynx 7.7提供多种更强大功能，只要搭配Altera的Stratix GX设计套件就能使客户确信其系统的高速SERDES线路能够正常运作。」　　 　　　「Xilinx致力为客户提供先进的连结解决方案，HyperLynx 7.7新功能使客户更容易导入我们的10Gbps RocketIO™技术。」Xilinx策略公关资深经理Jasbinder Bhoot表示，「我们与Mentor Graphics的合作很密切，这使双方共同客户得以充份利用该技术的优点。」　　 　　　设计套件　　　为进一步推广SERDES和其它新出现的联机标准，Mentor Graphics持续与主要的半导体组件和FPGA供货商合作，共同提供更多种技术 (USB、PCI-X、DDR) 和特定半导体组件 (例如Xilinx RocketIO和Altera Stratix GX) 专用的设计套件。这些套件包含模型、参考设计和设计说明，它们让工程师能够立即以新技术展开设计工作。　　 　　　支持所有主要的电路板布局工具　　　 HyperLynx兼容于Mentor所有电路板设计流程，包括Board Station® Series、Expedition™ Series以及PADS电路板设计环境，另外它也兼容于Cadence、Altium和Zuken的电路板布局系统。　　 　　　价格与供应时程　　 　Mentor Graphics已开始供应HyperLynx 7.7版，入门版售价从4,133美元起，全功能版售价则为39,200美元。Mentor Graphics还另外提供单机使用授权 (node locked) 以及浮动授权 (floating license)。 ::::::English Description:::::: Mentor Graphics® Corporation (Nasdaq: MENT), the market and technology leader in printed circuit board (PCB) design solutions, today announced the immediate availability of HyperLynx® 7.7, the latest version of its powerful and easy-to-use tool suite for pre- and post-layout signal integrity (SI)...