EDA Design Page 190

::::::English Description::::::  National Instruments Multisim software combines intuitive capture with powerful simulation to quickly, easily, and efficiently design and validate a circuit. With NI Multisim, you can quickly build a schematic with a comprehensive component library and emulate circuit behavior using the industry-standard SPICE simulator. Multisim provides an easy-to-use interface to SPICE, ensuring accurate and immediate simulation results.Professional designers can uncover flaws earlier in the design process, reducing prototype errors and time to market.You can purchase Multisim as a complete, integrated design and test platform to seamlessly transfer schematics to layout in NI Ultiboard software and incorporate real-world measurements and instrument control in the NI LabVIEW graphical development environment. Product:NI Circuit Design Suite Pro 10.1 Lanaguage:english Platform:Winxp/Win7 Size:366MB

Mentor.Graphics Board Station XE flow 2007.2 最新发布 BSXE2007.2 包括两个 flows: Board Station XE Flow 和 Board Station RE Flow.  Board Station XE 可制造性设计　　可制造性和可生产性设计一直是与PCB设计紧密联系的部分，有时候设计师需要更多的去控制生长数据。在以往，设计师不得不使用多个程序来建立原理图、PCB和产生设计数据。为了让以上流程更加简易，Mentor Graphics推出了基于AutoActive技术的一个整合的加工数据生成和验证环境－FabLink XE。他允许用户在PCB或者PCB拼板阶段控制生产数据，因此设计和生产数据可以更加紧密的结合起来。FabLink XE提供一个单独的标准拼板建立、编辑环境，并且也提供板级编辑功能，包括细节数据查看、可搜索的PDF文档输出、铜箔平衡、光绘和钻孔数据查看能。FabLink XE能够作用到三个设计数据阶段：制造数据准备阶段、制造数据输出阶段和文档阶段。 主要特性：　　基于AutoActive技术的拼板设计环境；　　整合后的高级功能简单易学；　　高效并且可重复设计不同拼板方案；　　可产生生产数据并且与源设计文件对比；　　在PCB布局布线阶段提供全程的用户自定义的生产规则检查功能，减少设计反复． Board Station RE 无网格自动布线环境　　Mentor Graphics公司最新开发的无网格布线工具AutoActive RE系列产品，采用了一种全新的AutoActive布线算法，集成于Mentor Graphics系列PCB设计工具中。Auto Active RE系列产品的主要特点在于可以帮助设计者解决新一代 PCB板设计中由于广泛采用新工艺的器件封装（COB、CSP、BGA）和新的印刷电路板制造工艺带来的微孔（Mircovia）、盲孔(blind via)、埋孔(buried via) 所带来的传统无网格器无法应付的挑战，解决了布线布通率以及可加工性等问题。采用的全新布线算法，使高密度PCB板的布线速度和布通率大大提高，同时具有极强的交互式布线能力，能够最大限度地缩短PCB板布线时间，满足用户对布线器性能的要求。 主要特性：　　器件放置(Placement)：　　以允许的最小间距放置器件；　　在放置器件时，自动、动态推挤器件和已布网线；　　移动器件进入已布线区时，系统自动重布该器件已布网线；　　移动成组器件，已布线与器件组同时移动；　　相同布局电路复制；　　Advanced Packaging与Manafacturing　　智能扇出：BGA、CSP、COB；　　微孔（Mircovia）放置；　　支持埋孔、盲孔；　　高速信号(High Speed)：　　支持高速布线规则与布线；　　支持串扰信号的评估；　　支持网线的交互式和自动调整；　　布线(Routing)：　　基于无网格的交互式和自动布线；　　最快的自动布线能力和布通率，以及最佳的可加工性能；　　实时的45度布线；　　完善的总线布线；　　变线宽布线；　　差分对线布线； ::::::English Description:::::: Board Station XE flow 2007.2 released by Mentor The BSXE2007.2 release includes two flows:  the Board Station XE Flow and the Board Station RE Flow.   Board Station XE gives Board Station customers quick and easy access to the most advanced PCB layout technology available. Tightly integrated in the overall design flow, Board Station XE combines the power of leading-edge autorouting technology with interactive editing capabilities in a single, powerful and easy-to-use design environment. By leveraging the ‘AutoActive’ platform, the...

Altera为FPGA、CPLD和结构化ASIC器件提供Quartus® II 设计软件。 Quartus® II 设计软件提供了一套最先进的工具，用于系统级设计、嵌入式软件编程、FPGA和CPLD设计、综合、布局布线、验证以及器件编程。Quartus II软件支持所有Altera的最新器件系列。 SOPC Builder是一个自动系统开发工具，它极大地简化了创建高性能可编程片上系统（SOPC）设计任务。SOPC Builder目前包含在Quartus II和Quartus II网络版软件产品中。 ModelSim®-Altera软件是Model Technology™ ModelSim仿真软件的Altera专用版本，支持行为级仿真和VHDL 或Verilog硬件描述语言(HDL)的仿真激励。 Nios® II集成开发环境(IDE)是一个图形化用户界面（GUI），在这个开发环境里面可以完成所有Nios II嵌入式处理器软件开发任务，包括编辑、编译、管理和调试嵌入式软件程序。 ::::::English Description:::::: Altera now provides the Quartus® II design software for FPGA, CPLD, and structured ASIC devices as part of the Altera® Subscription Program or  via download from the Altera web site as the Quartus II Web Edition software.  Quartus® II design software provides the most advanced suite of tools for system-level design, embedded software programming, FPGA and CPLD design, synthesis, place-and-route, verification, and device programming. Quartus II software supports all of Altera s latest device families. SOPC Builder is an automated system development tool that dramatically simplifies the task of creating high-performance system-on-a-programmable-chip (SOPC) designs. The ModelSim®-Altera software is an Altera-specific version of the Model Technology™ ModelSim...

Altera发布Modelsim 8.0，延续效能优势 Product:Altera Modelsim 8.0 Lanaguage:English Platform:/WinNT/2000/XP Size:168MB

::::::English Description:::::: Digital signal processing (DSP) system design in Altera® programmable logic devices (PLDs) requires both high-level algorithm and HDL development tools. Altera s DSP Builder integrates these tools by combining the algorithm development, simulation, and verification capabilities of The MathWorks MATLAB and Simulink system-level design tools with VHDL synthesis, simulation, and Altera development tools. DSP Builder shortens DSP design cycles by helping you create the hardware representation of a DSP design in an algorithm-friendly development environment. The existing MATLAB functions and Simulink blocks can be combined with Altera DSP Builder blocks and Altera intellectual property (IP) MegaCore® functions to link system-level design and implementation with DSP algorithm development. DSP Builder allows system, algorithm, and hardware designers to share a common development platform....

Additional Enhancements to Quartus II Software Version 8.0 * New tasks window: Provides an interactive design flow console that guides users through the FPGA design flow.SOPC Builder: Offers support for incremental compilation and adds key intellectual property (IP) blocks to its design library, including JTAG and SPI interfaces. * Enhanced FPGA I/O planning: Accelerates board development with added pin-swapping capabilities in the Pin Planner. * New IP advisor: Provides design-specific guidelines and recommendations for successful use of Altera’s PCI Express and DDR3 IP. * MegaCore® IP Library: Integrated in Quartus II software, making it easier for users to access Altera’s portfolio of IP cores. New additions with this release include PCI Express Gen2 hard IP, five new video and image...

nLint is a comprehensive HDL design rule checker fully integrated with the Verdi and Debussy debug systems. The Debussy system accelerates users understanding of complex designs to improve design, verification, and debug productivity. nLint adds the ability to fully analyze the HDL for syntax and semantic errors. nLint helps designers create correct HDL code by performing source code checks to ensure conformance with design rules such as synchronous design, clocking scheme, naming conventions, and testability. nLint helps uncovers errors early to reduce simulator, synthesizer, and ATPG run time and to reduce debug time. With nLint, users more easily create readable and maintainable code. They can enforce coding standards across design teams to achieve design re-use goals. nLint operates on design data...

::::::English Description:::::: Novas Design Comprehension Solutions Novas orchestrates a collection of leading-edge solutions that ease design comprehension throughout the verification flow, from systems to silicon.  Our debug systems reduce the time it takes to understand complex logic, giving you more time to spend on adding value to your design. Our new visibility enhancement products optimize verification resources by reducing the amount of data required to gain full visibility into design behavior, cutting simulation and emulation run times, reducing disk space requirements, and enabling effective silicon debug. Novas design comprehension solutions include: Debug Automation to accelerate tracing of causes and effectsProduct:Novas 2007.10 Linux Lanaguage:english Platform:Winxp/Win7 Size:679MB

SPD （Signal Processing Designer）仿真软件是 CoWare Inc.公司的产品，原名为SPW（Signal Processing Worksystem），它提供了面向电子系统的模块化设计、仿真及实施环境，是进行算法开发，滤波器设计，C 代码生成，硬/软件结构联合设计和硬件综合的理想环境。SPW的一个显著特点是他提供了HDS接口和MATLAB接口。MATLAB里面的很多模型可以直接调入 SPW，然后利用 HDS 生成 C 语言仿真代码或者是 HDL 语言仿真代码。SPD 通常可以应用于无线和有线载波通信、多媒体和网络设计与分析等领域。 它还具有以下技术特点： 1、 高效便捷的仿真手段：它用 C 语言开发，仿真效率高，同时，他提供图形化的配置仿真界面，友好的消息显示机制。而且可以在不需要用户干预的情况下进行多速率、动态调度的仿真处理。 2、 多种建模方式支持：只要是 C/C++兼容的建模，系统都可以提供支持，其建模参数可以是 C 兼容的变量表达式语言定义的复杂函数。 3、 大规模的标准数据模型，可支持 XML、关系数据库，并提供 TCL、C++等编程接口。  4、 丰富的构件库，并支持在原有构件库上的编程微调，直接提供 C 源码的编辑和编译环境。 5、 强大的分析和管理工具，可自动生成信噪比曲线，误码率曲线等。 6、 提供从系统建模到芯片级硬件设计的自动化功能。 SPD作为专业的DSP仿真设计开发工具，主要应用在电子设计、通信设计和芯片设计领域，对移动通信系统也提供了强大的支持，适合做底层开发和仿真。但同OPNET一样，它是一款专业性极强的软件，入门难度较高，同时，作为成熟和专业的商业软件，其价格不菲。 ::::::English Description:::::: CoWare Signal Processing DesignerImplementing Algorithms for Platform-Driven ESL Design Highlights Industry s fastest, production proven signal processing simulator Fully supported on Windows and Linux 4000+ models with source code Unique standards reference libraries Fully integrated with MATLAB® and Catalytic MCS tools Fully integrated into CoWare platform-driven ESL design solution RTL cosimulation support for Cadence Incisive® and Mentor Modelsim® RTL code generation for Synopsys DesignCompiler® and Cadence Encounter® Analog-Mixed Signal (AMS) cosimulation with Cadence Incisive® One-click analysis Powerful polymodeling...

Celoxica DK design suite提供以基于ANSI-C的Handel-C语言为基础的高阶设计方法，可在硬件中快速设计和实现复杂的运算法，除了先进的合成及时序评估工具外，DK的区域和延迟分析也可为快速最佳化提供布局前的早期时序和区域评估。该设计工具除了能输出特定FPGA平台EDIF格式外(包含Xilinx,Altera,Actel大部分的芯片)，它能输出结构化的Verilog和VHDL，并保留Handel-C原始码的层次性，因此用户能利用传统的仿真工具来除错Verilog或VHDL输出。HDL输出能用于FPGA/可程序平台，也可用于ASIC工具流程。Celoxica DK将C语言设计到FPGA的流程和方法最佳化，可让软件工程师、硬件设计者及系统架构设计师维持高性能的FPGA方案，并同时加速高可靠性、高速通讯的设计，以及从概念到实现的ASIC替代方案。 ::::::English Description:::::: The DK Design Suite software is a complete ESL design environment for ANSI-C using Handel-C. It provides the benefits of system-level design using C-based design languages to FPGA and SoC. This includes system co-design and co-verification capabilities as well as C-to-RTL and direct C-to-FPGA synthesis. Better designs, faster Specify, design and model systems in C Rapidly explore, simulate and verify diverse HW-SW architectures Find optimal partitions Synthesize directly to FPGA or RTL using the industry’s most widely used C-synthesis technology Algorithm acceleration The DK Design Suite enables designers to quickly and efficiently accelerate software algorithms and system bottlenecks in parallel hardware Sequential C algorithms can be migrated to a parallel hardware implementation using...