EDA Design Page 195

* FAST-Quickly visualize your complex HDL Design * Intuitive-Designed by EEs for EEs * Correct-Sunburst Design Rule checking, gets your design correct before simulation * Yours- Don\’t design our way, design it your way. Graphical or Text, it\’s your choice * Fast graphical design visualization * Support for incomplete designs * Popular text editor emulation Vi vs Emacs? How about both? * Automatically place modules correctly in your design * annotate thirdparty tools for easy visualization of the problems * Robust Command Line Interface APIProduct:StelarTools HDLE 2005.1 Lanaguage:english Platform:Winxp/Win7 Size:46MB

　电路板设计解决方案市场和技术领导者Mentor Graphics宣布推出HyperLynx 7.7版，这套强大而易于使用的布局前和布局后讯号完整性仿真与分析工具包含多项生产力和技术增强功能，最适合支持PCI-Express、Hyper Transport、XAUI和SATA/SAS等最新的SERDES联机标准。　这是专门用于Mentor Graphics Vendor-Independent Flow 2006-IND2006的版本。　 　　「 高速数字设计实用手册」(High-Speed Digital Design: A Handbook of Black Magic) 一书作者Howard Johnson博士表示：「HyperLynx 7.7新增加任意线路图编辑器和先进的高速分析功能，不但产品变得更实用，操作也更简单。所有数字设计人员都应该购买、学习和使用这套工具。」　　 　　　新提供的生产力增强功能包括简单易用的「任意形状」(free-form) 传输线路编辑器，设计人员可于布局前利用它尝试各种设计 (what-if) 和发展设计约束条件，进而轻松地建立所需的SPICE和S参数模型。HyperLynx 7.7会将所有讯号损耗来源列入考虑，包括封装寄生参数、连接头和导孔损耗以及电路板的电阻性损耗和介质损耗。HyperLynx 7.7会透过一套易于使用的环境管理这些讯号完整性效应，这使其成为全世界应用最广泛的讯号完整性软件。HyperLynx 7.7版还采用Mentor Graphics独有的「导孔显示」(Via Visualizer) 技术，这对于电路板导孔的深入分析有很大帮助。其它技术增强部份还包括批次仿真、更简单的使用者界面、更多的SERDES眼形罩幕 (eye mask)、更强大的SPICE建模功能以及超过13,000种新增IBIS模型。这些增强功能都兼容于所有主要的电路板布局环境，硬件工程师可以更有效地分析10亿位等级 (multi-gigabit) 串行式电路板联机。　　 　　 　SERDES (SERialization/DE-Serialization) 　　　 SERDES是一种快速窜红的连结技术，它能利用速率高达每秒数千兆位的串行驱动器和接收器将半导体组件和FPGA连接在一起。SERDES讯号是透过差动对传输资料，而非采用传统的宽总线架构，零件之间的资料速率最高达10 Gbps。除了资料产出大幅提升之外，SERDES还能减少电路板绕线面积、电路板厚度以及零件和连接头的接脚数。　　 　　　「对许多工程师和电路布局设计人员而言，印刷电路板的SERDES联机设计与分析是一种全新概念。」Mentor Graphics副总裁暨系统设计部门总经理Henry Potts表示，「新推出的HyperLynx不但简化设计作业，还提供完整的布局前和布局后分析能力，现在将有更多使用者可以利用这种联机技术发展效能更高的系统。」　　 　　　主要FPGA厂商的评论　　　「视讯和影像处理等应用都已采用PCI-Express等高速串行联机技术。」Altera的EDA厂商公关主管James Smith表示，「HyperLynx 7.7提供多种更强大功能，只要搭配Altera的Stratix GX设计套件就能使客户确信其系统的高速SERDES线路能够正常运作。」　　 　　　「Xilinx致力为客户提供先进的连结解决方案，HyperLynx 7.7新功能使客户更容易导入我们的10Gbps RocketIO™技术。」Xilinx策略公关资深经理Jasbinder Bhoot表示，「我们与Mentor Graphics的合作很密切，这使双方共同客户得以充份利用该技术的优点。」　　 　　　设计套件　　　为进一步推广SERDES和其它新出现的联机标准，Mentor Graphics持续与主要的半导体组件和FPGA供货商合作，共同提供更多种技术 (USB、PCI-X、DDR) 和特定半导体组件 (例如Xilinx RocketIO和Altera Stratix GX) 专用的设计套件。这些套件包含模型、参考设计和设计说明，它们让工程师能够立即以新技术展开设计工作。　　 　　　支持所有主要的电路板布局工具　　　 HyperLynx兼容于Mentor所有电路板设计流程，包括Board Station® Series、Expedition™ Series以及PADS电路板设计环境，另外它也兼容于Cadence、Altium和Zuken的电路板布局系统。　　 　　　价格与供应时程　　 　Mentor Graphics已开始供应HyperLynx 7.7版，入门版售价从4,133美元起，全功能版售价则为39,200美元。Mentor Graphics还另外提供单机使用授权 (node locked) 以及浮动授权 (floating license)。 ::::::English Description:::::: Mentor Graphics® Corporation (Nasdaq: MENT), the market and technology leader in printed circuit board (PCB) design solutions, today announced the immediate availability of HyperLynx® 7.7, the latest version of its powerful and easy-to-use tool suite for pre- and post-layout signal integrity (SI)...

::::::English Description:::::: Mentor Graphics® Corporation (Nasdaq: MENT), the market and technology leader in printed circuit board (PCB) design solutions, today announced the immediate availability of HyperLynx® 7.7, the latest version of its powerful and easy-to-use tool suite for pre- and post-layout signal integrity (SI) simulation and analysis. HyperLynx 7.7 includes significant productivity and technology enhancements targeted at classic high-speed bus technologies, as well as the rapidly emerging SERDES (SERialization/DE-Serialization) interconnect standards for connecting serial drivers and receivers. “I use HyperLynx because it is one of the few accurate circuit simulators with coupled lossy-line models and an integrated 2D field solver,” said Dr. Eric Bogatin, industry expert and author of Signal Integrity Simplified. “Plus, it is far and away the quickest...

Sonnet SUITE PRO 11.54提供面向3D平面高频电路设计系统以及在微波、毫米波领域和电磁兼容/电磁干扰设计的全套解决方案。通过提供高性能的EDA软件和专业的技术支持服务，帮助客户设计世界一流的产品。Sonnet SUITE PRO应用于平面高频电磁场分析，频率从1MHz 到几千GHz。主要的应用有：微带匹配网络 、微带电路、微带滤波器、带状线电路、带状线滤波器、过孔（层的连接或接地） 、偶合线分析、PCB板电路分析、PCB 板干扰分析、桥式螺线电感器 、平面高温超导电路分析、毫米波集成电路（ MMIC） 设计和分析 、 混合匹配的电路分析 、HDI 和LTCC 转换、 单层或多层传输线的精确分析、 多层的平面的电路分析 、单层或多层的平面天线分析 、平面天线阵分析、平面偶合孔的分析等。 定位于满足现在要求苛刻的挑战平面(3D平面)电路和天线设计人员的高频电磁设计软件. 支持microstrip, stripline, coplanar waveguide, 单多层PCB平面电路. 一、 Sonnet 软件的模块化。如同上图中看到的，Sonnet是由各种模块有机地结合在一起。包括预处理、分析求解器和后处理组成。预处理包括 dxfgeo、gds、ebridge转换模块和xgeom图形化电路编辑器；分析求解器由em和emlets组成，是软件的核心模块；后处理由emvu、patvu和emgrath三个模块组成。 二、 Sonnet提供全套集成的任务工具条 从单个的任务工具条, 你将能运行任何Sonnet程序。工作时，Sonnet任务工具条将为各模块之间提供很好的联系 。   ::::::English Description:::::: Sonnet Suite Release 11 3D Planar High-Frequency Electromagnetic Software Sonnet suites 11.54 of high-frequency electromagnetic (EM) Software are aimed at today s demanding design challenges involving predominantly planar (3D planar) circuits and antennas. Predominantly planar circuits include microstrip, stripline, coplanar waveguide, PCB (single and multiple layers) and combinations with vias, vertical metal sheets (z-directed strips), and any number of layers of metal traces embedded in stratified dielectric material. The Sonnet Suites develop precise RF models (S-, Y-, Z-parameters or extracted...

::::::English Description:::::: WELCOME TO PANTHEON, the next level for PCB/Hybrid/RF design engineering. As a complete design system, Pantheon offers in one application the same advanced features that others offer in multiple applications; geometry generation, component placement and routing, area fill, testpoints, split power planes, RF and hybrid design, and artwork creation/verification. Not only does Pantheon offer artwork creation and verification, it also offers the industry s only true double verification system in which the artwork is checked based on manufacturing rules, ensuring that the manufactured design will have zero defects. With the integration of multiple applications abilities into one highly functional application, Pantheon increases productivity to previously unreachable goals, while keeping design time and cost to a minimum. Pantheon s solid...

::::::English Description:::::: Electromagnetic Design System (EMDS) is a complete solution for electromagnetic simulation of arbitrarily-shaped, passive three-dimensional structures. It makes full 3D EM simulation an attractive option for designers working with RF circuits, MMICs, PC boards, modules, and Signal Integrity applications. It provides the best price/performance, 3D EM simulator on the market, with a full 3D electromagnetic field solver, a modern solid modeling front-end, and fully automated meshing and convergence capabilities for modeling arbitrary 3D shapes such as connectors, machined parts, components, bond wires, antennas, and packages. EMDS also comes with integration into Agilent s Advanced Design System (ADS), giving RF and microwave engineers access to the most comprehensive EM simulation tools in the industry. Product:Agilent Electromagnetic Design System (EMDS)...

::::::English Description:::::: The CoreConsole IP Deployment Platform (IDP) and block stitcher has been developed to enable designers to quickly assemble system-level designs and to simplify the construction of a processor subsystem and assembly of IP blocks within a design. The CoreConsole IDP is a front-end design entry tool that enables IP blocks to be stitched together into synthesizable and simulatable RTL that can be exported into Actel’s world-class Libero IDE FPGA development tool suite. The CoreConsole IDP  enables users to focus on the system rather than individual components, allowing them to evaluate system-level performance earlier in the design process and reduce overall development time. Product:Actel CoreConsole 1.4 Lanaguage:english Platform:Winxp/Win7 Size:197MB

Libero IDE offers the latest and best-in-class FPGA development tools from leading EDA vendors such as Mentor Graphics, SynaptiCAD, and Synplicity. These tools, combined with Actel developed tools allow you to quickly and easily manage your Actel FPGA designs. An intuitive user interface and powerful design manager guides you through the process while organizing design files and seamlessly managing exchanges between the various tools. Libero IDE Software Features: Powerful project and design flow management Full suite of integrated design entry tools and methodologies: CoreConsole configured processor and DirectCore IP subsystem creation SmartGen configured common and bus based cores HDL and HDL templates User-defined blocks creation flow for design re-use Actel macro cells ViewDraw Schematic Capture  SmartDesign graphical block subsystem creation...

Actel Libero IDE 8.3 最新释放,Actel创新的SmartDesign功能可简化系统级设计 Actel Corporation 宣布了版本8.3 的它的 Libero 集成设计环境(IDE) 为 FPGA 设计。新版本提供 SmartDesign, 使用户设计在一个更高的水平抽象。新工具随员支持所有Actel 的FPGAs, 包括并且基于闪光的, 低功率ProASIC3 和5 微瓦特Actel 园屋顶的小屋FPGAs, 单片Actel 融合PSC (可编程序的系统芯片) 。 Actel公司为履行其提供和支持高功效解决方案的承诺，全面提升了其Libero集成设计环境 (IDE) 的效能，进一步简化采用其现场可编程门阵列 (FPGA) 产品进行系统级设计的过程。Actel的Libero IDE v8.3现备有名为SmartDesign的全新设计输入项目功能，可让用户在更高的抽象层面完成设计，大大缩短FPGA的设计和开发时间，从而加快客户产品的面市。升级的工具套件支持Actel所有FPGA产品，包括以 Flash 为基础的低功耗ProASIC3和静态功耗仅为5µW的IGLOO FPGA，以及混合信号电源管理FPGA，即单芯片Fusion PSC (可编程系统芯片)。 SmartDesign 是Libero IDE v8.3的一个关键功能，可让用户以图形化方式创建，然后自动抽象出各种基于构件的系统设计并转换成已完成综合 (synthesis-ready) 的VHDL或Verilog部件。这种以图形化方式实现的构件设计输入项目功能支持Actel丰富的DirectCore 和SmartGen IP核库中的各种预制构件，同时也支持采用HDL或 Synplify® DSP生成的用户定制构件，以及用Actel的CoreConsole工具生成的处理器子系统。 Actel产品市场拓展副总裁Rich Brossart称：“Libero以其精确且易于使用的SmartPower功耗分析工具取胜，能协助设计人员应对越来越严格的功耗要求。Libero IDE v8.3工具套件的增强功能代表了我们简化设计和支持高功效应用的最新创新成果。无论用户正在设计ARM处理器、基于Fusion技术的子系统还是使用我们的低功耗IGLOO 器件来设计便携式应用，配有SmartDesign的Libero IDE v8.3均可加快其设计过程，为用户提供能‘正确构建’的保证。” 基于SmartDesign构件的系统级设计环境 创新的SmartDesign具有输入源文件部件的功能，比如将SmartGen和 CoreConsole配置的IP核和处理器核、HDL模块、Actel提供的宏单元，以及Libero生成的构件能以图形化方式组合在一起，并以模块化视图显示在构件视图中的白板“画布” (canvas) 上。SmartDesign提供名为“catalog”的列表功能，能够列出广泛的IP核、宏、HDL模板，以及总线接口；让用户选择所需的元素，然后拖放到“画布”中。因此，SmartDesign利用现有设计的可重用性，为将来采用System Verilog语言、DSP、混合软件/硬件模块来实现的模块化设计铺路。 除了采用SmartDesign设计外，还可通过“SmartGuide”功能为用户建议与设计相配的兼容总线和IP核，这项功能也可用作设计规则检查，确保构建的连接正确。当设计完成后，将生成出已进行综合的HDL源代码文件。由于许多连接都由 SmartDesign中的SmartConnect 功能自动完成，因此Libero IDE v8.3能够为设计人员节省时间和减少错误。 新功能简化Fusion电源管理设计 Libero IDE v8.3加入了升级的FlashPro 6.0软件，为Actel屡获殊荣的混合信号FPGA系列产品Fusion带来额外的支持。配合使用FlashPro 编程器，新版的IDE 软件能够进一步简化Actel的 IGLOO/e、ProASIC3和 Actel Fusion器件的编程。FlashPro中名为FlashPoint的新增功能允许用户独立于Libero 或Designer来修改和编辑FlashROM的安全设置，从而增强设计修改的灵活性。这样，用户就不必通过综合重新运行设计，也省去了布局布线和程序文件生成的工序，大大地缩短了总体的设计时间。 对于Fusion产品，FlashPro的FlashPoint功能可进一步支持用户对Fusion内嵌 Flash 存储器的独立编程。用户可高效地重新编程存储在内嵌 Flash 存储器的电源管理的模拟参数和系统代码。 Product:Actel Libero IDE 8.3 Lanaguage:English Platform:/WinNT/2000/XP Size:760MB

Sentaurus Process is an advanced 1D, 2D, and 3D process simulator for developing and optimizing silicon and compound semiconductor process technologies. Created by combining the best-in-class features from Synopsys and former ISE TCAD products, together with a wide range of new features and capabilities, Sentaurus Process is a new-generation process simulator for addressing the challenges found in current and future process technologies. Equipped with a set of advanced process models, which include default parameters calibrated with data from equipment vendors, Sentaurus Process provides a predictive framework for simulating a broad range of technologies from nanoscale CMOS to large-scale high-voltage power devices. Sentaurus Process is part of the comprehensive Synopsys suite of core TCAD products for multidimensional process, device, and system...