EDA Design Page 180

Flomerics has released Version 7 of its Flotherm electronics thermal analysis software featuring a new Response Surface Optimization capability that Flomerics believes is unrivalled in computational fluid dynamics (CFD) analysis software. Earlier versions of Flotherm included a sequential optimization capability allowing users to specify combinations of design parameters and iterate sequentially towards the best design. The new Response Surface Optimization goes further by fitting a 3D surface to the entire design space, enabling engineers to visualize the complete interaction of the design parameters with the design goal as well as identifying the optimum to a greater degree of accuracy. The user begins Flotherm’s optimization process by defining design goals in the form of a “cost function”, and the ranges over...

JMAG is a simulation software for electromechanical design and development. Many companies and universities have supported and used JMAG since 1983. JMAG can accurately capture and quickly evaluate complex physical phenomena inside of machines. Users inexperience and experienced in simulation analysis can easily perform the simple operations required to obtain precise results. MAG-Designer is a simulation software for electromechanical design striving to be easy to use while providing versatility to support users from conceptual design to comprehensive analyses.Product:JMAG Designer 3.4 Lanaguage:english Platform:Winxp/Win7 Size:474MB

Engineering BaseProduct:Engineering Base 3.1.1.13 Lanaguage:english Platform:Winxp/Win7 Size:816MB

Cadence Incisive Plan-to-Closure Methodology将支持Open Verification Methodology，OVM，OVM基于Cadence的Incisive  Plan-to-Closure URM模块和Mentor的先进验证方法学模块。product:Cadence Incisive Plan-to-Closure Methodology (IPCM) 6.0 Linux Lanaguage:English Platform:linux Size:164MB

PADS®, Mentor Graphics’ world-leading desktop PCB design tool, enables you to develop PCBs within a highly productive, scalable, and easy-to-use environment. PADS solutions cover the spectrum of PCB development, from schematic entry to manufacturing preparation. But, unlike other products, we’re not ‘one-size-fits-all.’ With PADS you buy what you need. PADS Suites, available in three configurations, are our newest solutions, tailored to meet the design needs of each individual.product:Mentor Graphics PADS 2007.3 with update2 Lanaguage:english Platform:Winxp/Win7 Size:565MB

FPGA Advantage is a complete Integrated Design Environment (IDE) targeting high-complexity FPGA device design. The FPGA Advantage IDE spans the RTL FPGA design flow featuring advanced design entry, verification, synthesis and implementation sub-flows. FPGA Advantage accelerates total product design with integration of FPGA IO design as well as bi-directional integration of the PCB design flow. FPGA Advantage provides an integrated HDL flow for designing your FPGAs. FPGA Advantage enables design creation, simulation with debug and analysis, synthesis, management and documentation as a smooth flowing operation from one step to the next. Each component of FPGA Advantage is a proven point tool, but the power comes from integrating these tools tightly together to create a unique HDL design methodology environment for...

Incisive Desktop Manager  Automated verification management Incisive Desktop Manager automates and guides the everyday deployment and visualization of verification tasks and results, increasing engineering productivity and reducing time to market.Cadence® Incisive® Desktop Manager accelerates verification plan execution by automating time-consuming manual tasks at block, chip, system, and project levels. It manages the everyday deployment of common verification tasks, together with visualization of the results. Incisive Desktop Manager also supports a coverage-based verification and debug methodology that increases coverage using incrementally-developed verification plans. Features/Benefits Speeds time to results by automating verification tasks Increases engineering productivity by managing regression tests and failures Enables visualization of coverage results product:Cadence Incisive Desktop Manager (EMGR20) 2.0 Linux Lanaguage:english Platform:Winxp/Win7 Size:397MB

Cadence® Incisive® Formal Verifier allows design teams to start RTL block verification months earlier than when using traditional simulation-based techniques. Its formal, assertion-based approach and exhaustive analysis capabilities ensure verification quality by pinpointing the source of bugs and detecting the corner-case errors that other methods often miss. Incisive Formal Verifier integrates easily into established design and assertion-based verification flows through its support of industry-standard languages. Features/Benefits * Speeds time to block design closure with early error detection, analysis, and debug * Reduces risk of re-spin by finding bugs that other verification approaches miss * Eases chip-level verification by delivering higher block-level verification quality * Leverages the same assertions as Incisive simulation, acceleration, and emulation technologies * Supports all industry-standard assertion...

Cadence® Incisive® Enterprise Specman Elite® Testbench uses executable specifications and designer-specified constraints to automate testbench generation, while simultaneously detecting misrepresentations of the specification. Its automated data and assertion checking speeds debug, while its functional coverage analysis capability drives verification using the Plan-to-Closure Methodology. Specman technology also supports industry-standard verification languages, compatible with both the Open Verification Methodology (OVM) and the e Reuse Methodology (eRM), so engineers can quickly and easily integrate it with established verification flows. With the Enterprise System-Level (ESL) Option, Specman technology can be extended to support hardware/software co-verification with pure software simulation-based flows as well as complete “in-system” flows via high-speed links to acceleration and emulation. Features/Benefits * Captures executable specifications to eliminate misrepresentations that can lead...

在采用现有 IP核创建系统级芯片(SoC)时，关键是在设计周期之初，在目标环境中快速地配置和验证IP核。在采用多个IP模块和诸如AMBA的芯片级总线进行设计创建时，设计人员需要能够轻易地完成将多个IP模块连接到总线上并进行配置，从而能够将精力集中在设计中新的逻辑电路上。采用了DesignWare IP 重用工具，IP的创建者可以将自己的IP以某种格式进行打包，这种格式将引导IP集成者完成IP的配置、实现和验证。这样，IP集成者就可以用若干小时，而不是若干天的时间来创建复杂的IP模式和子系统，并开始对它们进行验证，从而大大缩短了整个设计周期。 　　Synopsys为单个IP模块和基于IP的子系统提供了一整套的IP工具，使得IP的创建者和集成者能够轻易地创建和支持复杂的IP。 　　● coreBuilder -将IP有效打包 　　● coreConsultant -引导用户完成IP核的配置和集成 　　● coreAssembler -帮助用户创新和管理打包的基于IP的子系统，包括装配、配置和实现 ::::::English Description:::::: The Synopsys family of coreTools is a comprehensive set of intellectual property (IP) packaging and integration tools for use in a knowledge-based design and verification flow. The tools enable designers to realize maximum productivity gains when using IP in their desing. By using an IP-based design and verification flow with IP packaged for assembly, the risk configuration, and subsystem integration errors is virtually eliminated, and designers have seen over a 60% reduction in SoC or platform design time and achieve the highest QoR in the implementation of the design.The coreTool family includes:coreBuilder™ – a robust packaging tool that allows designers to capture the knowledge...