EDA Design Page 182

Artwork Mask, Modeling and User Interface Enhancements Save Time for RF Designers with Tight Deadlines and Budgets SANTA CLARA, Calif., July 31, 2008 Agilent Technologies Inc. (NYSE: A) today announced shipment of its Genesys 2008.07 release. The new Genesys release contains improvements to the reliability of artwork masks for electromagnetic (EM) verification and RF board manufacturing, along with modeling and user interface improvements. This functionality results in shorter design cycles with fewer iterations for RF designers with tight deadlines and budgets. The Genesys 2008.07 release reliably exports RF board mask and artwork files to a wider set of board fabricators, inexpensive rapid-prototyping machines and a variety of CAD/CAM software for physical product design. The release also includes a graphical artwork...

 Cadence Assura  3.20  是新一代深亚微米模拟和混合IC版图验证、 寄生参数提取以及分辩率增强可制造性解决方案。product:Cadence ASSURA 3.20 Linux Lanaguage:English Platform:/Linux Size:1.52G

VCS MX 2008.09 Linux  is the industry抯 most comprehensive RTL verification solution in a single product, providing advanced bug-finding technologies, a built-in debug and visualization environment and support for all popular design and verification languages including Verilog, VHDL, SystemVerilog and SystemC™. The VCS solution抯 advanced bug-finding technologies include full-featured Native Testbench, complete assertions and comprehensive code and functional coverage to find more bugs faster and easier. Additionally, the VCS Verification Library provides verification IP for today抯 most popular bus standards. By natively integrating these technologies within its unique, single-compiler architecture, the VCS solution delivers up to 5X faster verification performance compared with using multiple, stand-alone tools. The VCS solution抯 powerful debug and visualization environment minimizes the turnaround time to find and fix...

ynopsys, Inc. is the solutions leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/ . NOTE: Synopsys is a registered trademark and Magellan is a trademark of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their...

The installation instructions in this document are the most up-to-dateavailable at the time of production. However, changes might have occurred.For the latest installation information, see the product release notes ordocumentation.This document provides instructions for the UNIX, Linux, and Windowsplatforms. The document includes the following sections:Preparing for InstallationInstalling SpiceExplorer and WaveView Analyzer (UNIX and Windows)Invoking SpiceExplorer and WaveView Analyzer on WindowsInstalling the SX-CDS Link PackageInstalling the SX-DAIC Link PackageInstalling the SX-VSDE Link PackageViewing and Printing SpiceExplorer and WaveView AnalyzerDocumentation in Portable Document Format (PDF)Troubleshooting SpiceExplorer and WaveView Analyzer Installation onSolaris PlatformsUninstalling SpiceExplorer and WaveView AnalyzerCustomer Supportproduct:Synopsys SpiceExplorer 2008.03 SP1 Linux Lanaguage:english Platform:Winxp/Win7 Size:54MB

Synopsys Analysis and Debug products provide a unique approach to transistor-level verification that enables engineers to efficiently analyze and debug complex AMS systems-on-chips (SoCs). CustomExplorer addresses the need for an effective transistor-level debugging environment. The tools provide a netlist-driven debugging and visualization modules, and Custom WaveView with ACE scripting option completes the package. The environment provides front-to-back productivity solutions to speedup verification cycle and reduces total design cost.product:Synopsys SpiceExplorer 2008.09 Win Lanaguage:english Platform:Winxp/Win7 Size:9MB

he industry\’s first development tool to automatically generate Triple Module Redundancy (TMR) for re-programmable FPGAs. The Xilinx Triple Module Redundancy (XTMR) technology was developed to address the special needs of FPGAs in high-radiation environments. Originally designed for space applications and proven through numerous mission-critical projects, XTMR provides full SEU and SET immunity for any high reliability Virtex®-4 FPGA design.Device Family Support * Virtex-4 * Virtex-II * Virtex System Requirement * Windows 2000/XP Software Requirements * ISE® Foundation™ Software Key Features * Automatically builds XTMR into Xilinx FPGA designs, providing complete SEU and SET immunity * Supports all design entry methods, HDLs, and synthesis tools * Provides optional SRL16 extraction capability * Allows easy integration of custom-built TMR modules * Gives...

Synopsys\’ Leda® is a programmable design and coding guideline checker that delivers full chip mixed-language (Verilog and VHDL) and mixed representation (RTL & gate) capabilities to speed development of complex system-on-chip (SoC) designs. Leda’s pre-packaged rules greatly enhance a designer\’s ability to check HDL code for synthesizability, simulatability, testability, reusability, and RTL/gate signoff. Leda detects clock synchronization-related bugs, isolates hard-to-time circuits, verifies layout considerations and improves DFT for higher ATPG coverage. Leda comes prepackaged with rules to improve performance of Synopsys tools, such as VCS MX, DC and Formality. Key Benefits * Finds complex bugs, such as those associated with multiple clock domains using static analysis * Verifies consistency of design and SDC constraints for DC, PrimeTime and Astro *...

JMAG-Studio is an electromagnetic field analysis software package developed by JRI Solutions, Ltd. thatsupports the design and development of motors, actuators, circuit components, antennas and other electricand electronic products. It has been supported and used by many companies and universities since 1983.JMAG has a long track record of use for analyzing motors and other rotating devices.JRI Solutions is constantly improving JMAG-Studio by incorporating features suggested in from our usersand by using the latest technology developed through our research and accumulated analysis expertise.Product:JMAG Studio 9.0 Lanaguage:english Platform:Winxp/Win7 Size:144MB

ICX / TAU ICX® and ICX Pro provide an intuitive user interface for engineers to explore signal integrity solutions in their high-speed designs. Engineers learning signal integrity are offered a concise view of how things work, while those more seasoned are able to investigate signal integrity effects in their designs in great detail. Components are modeled using industry standard IBIS models, with support for virtually all IC model types, while simulations are provided by our proven ICX simulation technology. With a library of default IBIS models provided, engineers can begin evaluating high-speed design solutions easily and quickly. The Tau® board-level symbolic timing analysis tool performs comprehensive worst-case timing analysis and verification on designs using an advanced symbolic timing methodology, eliminating...