Simucad is a provider of circuit simulation and CAD software tools used in the design of analog, mixed-signal, and RF integrated circuits. The company was incorporated in Delaware in June 2004 as a spin-off from Silvaco Data Systems.[1] Simucad acquired ownership all of Silvaco\’s simulation and CAD products and intellectual property, most notably the SmartSpice circuit simulator[2].Product:SIMUCAD AMS 2008 Linux64 Lanaguage:english Platform:Winxp/Win7 Size:282MB
Silvaco TCAD 2008.09 tools start with understanding the physics of the basic semiconductor, dielectric, and conducting materials. The Virtual Wafer Fab technology simulation environment enables the ATHENA process technology simulators and the ATLAS device technology simulators to prepare, run, optimize, and analyze semiconductor experiments to achieve optimal process recipes and device targets.Product:Silvaco TCAD 2008.09 Win Lanaguage:English Platform:/win2000/winxp Size:344MB
Silvaco, inc. is a privately owned provider of electronic design automation (EDA) software[1] and TCAD process and device simulation software.[2] Silvaco was founded in 1984 by Dr. Ivan Pesic. It is headquartered in Santa Clara, California with 11 offices worldwide, and in 2006 the company had about 250 employees worldwide. Silvaco provides analog semiconductor process, device and design automation solutions in CMOS, bipolar, SiGe and compound technologies. Customers include leading fabless semiconductor companies, integrated semiconductor manufacturers, foundries, and universities worldwide.Product:Silvaco SIMUCAD IC CAD 2008.09 Win Lanaguage:english Platform:Winxp/Win7 Size:122MB
SmartSpiceRF employs a combination of Time-Domain Shooting and Frequency-Domain Harmonic Balance methods to provide accurate simulation of GHz range RF ICs. It accurately and efficiently simulates harmonic distortion, intermodulation products, gains, noise, oscillator’s phase noise in non-linear circuits using SPICE netlists. Key Features * Performs complete set of periodic and quasi-periodic steady-state analyses for large-signal and small-signal applications – each with full parametric sweep and Monte Carlo control parameters * Time-domain Shooting method to simulate periodic steady-state of highly nonlinear circuits * Time-Frequency domain Envelope analysis of circuits driven by digitally modulated sources * A complete set of digitally modulated signals is supported together with all SmartSpice models for large-signal, small-signal, noise, and parametric analysis * Provides simulations and measurements...
Silvaco SIMUCAD Logic 2008.09 WinProduct:Silvaco SIMUCAD Logic 2008.09 Win Lanaguage:English Platform:/win2000/winxp Size:81MB
Mentor Graphics Calibre 2008.3_25.16 Linux Calibre LVS Industry standard physical verification tool for layout versus schematic. Provides method for accurate device parameter extraction with integration to Calibre xRC Allows virtually unlimited capacity for hierarchical designs Offers easy-to-use automatic analysis and optimization of hierarchy for execution efficiency across all design styles Seamless interface within many design environments product:Mentor Graphics Calibre 2008.3_25.16 Linux Lanaguage:english Platform:Winxp/Win7 Size:513MB
::::English Description:::::: Timing closure in today advanced designs remains the number one challenge for designers today, especially at 90-nanometers (nm) and below. A trusted timing sign-off solution that accurately models and predicts silicon behavior is required to enable designers to quickly achieve timing closure. The Synopsys PrimeTime static timing analysis solution is the most trusted and advanced timing sign-off solution for gate-level designs. It is the industry de-facto gold standard for gate-level static timing analysis and is a key component of the Galaxy?Design Platform. With a wide breadth of sign-off analysis capabilities, the PrimeTime STA solution provides a comprehensive and unmatched environment for timing sign-off and serves as an industry yardstick for timing analysis and sign-off. It delivers to designers...
Timing closure in today advanced designs remains the number one challenge for designers today, especially at 90-nanometers (nm) and below. A trusted timing sign-off solution that accurately models and predicts silicon behavior is required to enable designers to quickly achieve timing closure. The Synopsys PrimeTime static timing analysis solution is the most trusted and advanced timing sign-off solution for gate-level designs. It is the industry de-facto gold standard for gate-level static timing analysis and is a key component of the Galaxy?Design Platform. With a wide breadth of sign-off analysis capabilities, the PrimeTime STA solution provides a comprehensive and unmatched environment for timing sign-off and serves as an industry yardstick for timing analysis and sign-off. It delivers to designers extensive timing...
::::::English Description:::::: Micro-Cap 9 is an integrated schematic editor and mixed analog/digital simulator that provides an interactive sketch and simulate environment for electronics engineers. Since its original release in 1982, Micro-Cap has been steadily expanded and improved. Micro-Cap 9, the eighth generation, blends a modern, intuitive interface with robust numerical algorithms to produce unparalleled levels of simulation power and ease of use. Nothing else comes close. Faster Algorithmic improvements, optimized code, and an integrated, seamless, analog/digital simulation interface contribute to the stunning speed of Micro-Cap 9. More powerful Numerous features contribute to Micro-Cap 9 s power. Among them are: Integrated schematic editor and simulator. Interactive editing and simulation Native digital simulator Transient analysis AC analysis – for investigating...
High-Level Algorithm Implementation for FPGAs and ASICs The Synplify DSP tool provides a unique high-level synthesis methodology that realizes significant productivity and portability advantages. System and algorithm designers can quickly capture complex algorithmic behavior using the Synplify DSP library. The Synplify DSP synthesis engine allows designers to automatically implement and explore area/speed optimized RTL implementations from a single model. This eliminates the burden of hand-coding functions and architectural optimizations and results in significantly faster design capture, speeds time-to-market, and enables rapid design exploration for improved quality and lower cost.product:Synopsys Synthesis Tools 2008.09 SP2 AMD64 Lanaguage:english Platform:Winxp/Win7 Size:277MB