EDA Design Page 203
LabVIEW NI SoftMotion offers the convenience of programming your motion profiles with a high-level function block API based on the Motion Control Library defined by PLCopen including function blocks for straight-line, arc, and contoured move types as well as function blocks for advanced operations like electronic gearing and camming. LabVIEW NI SoftMotion also features advanced functions for custom motion application design including trajectory generation, spline interpolation, position and velocity control, and encoder implementation. By combining LabVIEW NI SoftMotion with the new NI C Series drive interface modules for CompactRIO, you can take advantage of the RIO Scan Interface for simplified application development for single-axis and multiaxis coordinated motion. For applications that require functionality or features that are not available with...
National Instruments DIAdem is software for managing, analyzing, and reporting data collected during data acquisition and/or generated during simulations. NI DIAdem is designed to help you make informed decisions and meet the demands of today’s testing environments, which require quick access to large volumes of scattered data, consistent reporting, and data visualization. The DIAdem DataFinder, which is optimized for managing data from multiple sources and different formats, helps you correlate data based on its descriptive attributes – functionality previously reserved for only those with a customized data management system.Product:NI DIAdem 10.2 Lanaguage:english Platform:Winxp/Win7 Size:273MB
OverviewToday’s complex integrated circuit (IC) designs generate a vast amount of simulation data. CosmosScope™ turns that mountain of data into useful information. With powerful analysis and measurement capabilities, patented waveform-calculator technology, and scripting language based on the industry standard Tcl/Tk, CosmosScope offers unparalleled capability and flexibility to analyze design performance and ensure design quality. CosmosScope supports all Synopsys simulators: HSPICE®, NanoSim™, Saber® and SaberHDL. CosmosScope benefits * Supports all Synopsys simulation products with a single viewer including HSPICE, NanoSim Saber, and SaberHDL * Provides powerful Tcl/Tk-based scripting language for easy customization * Performs post-processing of analog and digital simulation results * Automatically annotates graphs with design information using true WYSIWYG graphics, including arrows, shapes and text * Annotates graphs with...
As technology feature sizes shrink, conductors get smaller, and supply voltages reduce, the corresponding current per scaled feature size increases exponentially. These changes cause power-rail IR (voltage) drop and electromigration (EM) effects that significantly degrade performance and might cause the circuit to malfunction. To eliminate such problems, Astro-Rail™ provides an accurate and design-stage comprehensive sign-off solution for power consumption, IR drop and EM analysis for advanced-technology designs. Astro-Rail is an important component of Synopsys?Milkyway™-based Galaxy™ solution. Using Synopsys?proprietary Dynamic-Macromodeling™ technology, Astro-Rail assists in reducing time to market and ensures reliability. In Astro-Rail, IR drop and EM analysis of million gate designs are completed in minutes. Astro-Rail provides sign-off quality analysis results within five percent tolerance of HSPICE® with Star-RCXT™ parasitic...
:::::English Description::::::Synopsys?JupiterXT™ design planning solution enables fast feasibility analysis for a preview of implementation results, and provides detailed floor planning capabilities for flat or hierarchical physical design implementation styles. Project leaders and physical designers of ASIC or COT designs benefit from the accurate prediction and production-proven convergence JupiterXT provides. Feasibility analysis is supported for incomplete netlists in the form of black boxes or early gate level netlists. Powerful placement algorithms incorporate designers?knowledge of black box content and produce routable floorplan results using autoshaping with full rectilinear support. If gate netlists are available, the placement algorithms apply a virtual flat approach that places hard macros and standard cells simultaneously. As more detailed design content is added to netlists as a result...
Synopsys, Inc. today announced that UMC has adopted Synopsys TetraMAX diagnostics to accelerate yield learning for designs that utilize the Synopsys DFT MAX scan compression automation solution. Rapid yield learning depends on the accuracy and efficiency of failure analysis, a manually intensive and time-consuming process of identifying the individual circuit in a design that could cause a device to fail. Using Synopsys TetraMAX diagnostics to perform this task automatically on DFT MAX-compressed scan patterns, UMC engineers were able to substantially decrease the time and effort required for failure analysis. \”As part of UMC\’s leading-edge manufacturing products and services, we are continuing to build upon our portfolio of robust rapid learning tools,\” said S. R. Sheu, Product Engineering Director at UMC....
Mentor Graphics Vendor-Independent Flow 2006-IND2006 Linux 完整的PCB设计解决方案，包含具有强大功能的布局和模拟工具的概略图定义 ::::::English Description:::::: Mentor Graphics Announces Precision RTL Plus for FPGA Synthesis – Vendor-Independent Flow 2006 Linux(IND2006) New Features for IND2006 ICX The following are the new features for ICX 3.6.0-ICX Pro simulator -ICX Pro Waveform Analyzer with FFT -Allegro 15.5 interface support -Support for ndd-files with long property values I/O Designer-Concurrent design of FPGA and PCB through bi-directional communication between FPGA and PCB design environments-Optimize FPGA pin assignments for PCB routing and system performance -Automatic symbol generation and fracturing -I/O design data management -FPGA constraints verification including Timing constraints -Configurable power and ground PCB signal names -View of layout placement for I/O optimization –Automatic unravel nets -Mapping between HDL and PCB signal names -Import...
>::::::English Description:::::: Mentor Graphics Announces Precision RTL Plus for FPGA Synthesis – Vendor-Independent Flow 2006(IND2006) New Features for IND2006 ICX The following are the new features for ICX 3.6.0-ICX Pro simulator -ICX Pro Waveform Analyzer with FFT -Allegro 15.5 interface support -Support for ndd-files with long property values I/O Designer-Concurrent design of FPGA and PCB through bi-directional communication between FPGA and PCB design environments-Optimize FPGA pin assignments for PCB routing and system performance -Automatic symbol generation and fracturing -I/O design data management -FPGA constraints verification including Timing constraints -Configurable power and ground PCB signal names -View of layout placement for I/O optimization –Automatic unravel nets -Mapping between HDL and PCB signal names -Import PCB design wizard -Full synchronisation wizard -DMS corporate...
Raphael NXT is a true three-dimensional (3D) capacitance extractor that provides silicon-accurate self and coupling capacitances for IC design. Equipped with an ultrafast extraction engine, Raphael NXT complements Star-RCXT by extracting 3D capacitances of critical nets, cells, or blocks on the full-chip level. Raphael NXT supports the latest processes that include conformal dielectric layers, trapezoidal conductors, lithography effects, and metal fill, providing an accurate representation of the complex geometries found in interconnect structures. As a result, capacitance values extracted by Raphael NXT are closely correlated with Raphael, the gold-standard reference field solver, or silicon measurements. [b]Benefits[/b] Extraction of field solver朼ccurate capacitance for critical nets, cells, and blocks on the full-chip level Accounts for detailed process effects predominant in leadingedge nanoscale...
ynopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today announced that Cypress Semiconductor Corp. has successfully taped out its West Bridge™ Antioch™ peripheral controller multimedia 3G/3.5G mobile phone integrated circuit (IC) using the Synopsys Galaxy™ design platform RTL-to- GDSII low-power solution, including the PrimeRail dynamic power network analysis solution. The multithreshold CMOS (MTCMOS) power gating feature in the Galaxy design platform enabled Cypress to complete its ultra-low-power design with world-class performance and optimized standby current. PrimeRail, a key component of the Galaxy design platform, enabled peak current analysis for the multiple power domains of the Power Gating-based design during physical implementation. \”For our mobile phone chip design, we needed a solution that could address peak current problems...