EDA Design Page 203

The NI Motion Assistant speeds up the development and testing of motion applications by providing an easy-to-use interactive environment. You can convert any application developed using the NI Motion Assistant to C code or NI LabVIEW VIs for final machine deployment, eliminating the need for any additional programming. The NI Motion Assistant offers the ability to import motion profiles created in CAD or drafting packages using the widely accepted DXF file format. Using this feature with the NI patent-pending smart-contouring algorithm, you can implement precise motion profiles for cutting or scribing applications. The NI Motion Assistant works with National Instruments plug-in motion controllers for blended trajectory control and fully coordinated circular, linear, point-to-point, gearing, and vector-space control. It offers a...

::::::English Description:::::: HSIMplusHSIMplus™ 2007.03 Linux is a fully-integrated suite of tools for the design and verification of nanometer ICs, built upon the production-proven HSIM hierarchical Fast-SPICE simulator. HSIMplus exceeds the capabilities of competitor’s Fast-SPICE simulators, by providing a complete solution for analysis of the effects that dominate performance and reliability in silicon at 90nm and 65nm process nodes. HSIM® delivers superior performance and capacity over traditional SPICE-based simulators, by applying two innovative and proprietary techniques: Hierarchical Storage and Isomorphic Matching   Hierarchical StorageTraditional SPICE-based simulators employ matrix-solving algorithms that must flatten the hierarchy that designers build into their circuit, in order to simultaneously solve for all node voltages and branch currents at every time step in a simulation. The hierarchical solver...

:::::: HSIMplusHSIMplus™ 2007.03 is a fully-integrated suite of tools for the design and verification of nanometer ICs, built upon the production-proven HSIM hierarchical Fast-SPICE simulator. HSIMplus exceeds the capabilities of competitor’s Fast-SPICE simulators, by providing a complete solution for analysis of the effects that dominate performance and reliability in silicon at 90nm and 65nm process nodes. HSIM® delivers superior performance and capacity over traditional SPICE-based simulators, by applying two innovative and proprietary techniques: Hierarchical Storage and Isomorphic Matching   Hierarchical StorageTraditional SPICE-based simulators employ matrix-solving algorithms that must flatten the hierarchy that designers build into their circuit, in order to simultaneously solve for all node voltages and branch currents at every time step in a simulation. The hierarchical solver in HSIM...

。Complete and accurate cell characterization is essential for automated implementation and verification of complex system-on-chips (SoC). Capturing sufficiently accurate timing, power and signal integrity information, as well as operating condition variability for 90-nm and 65-nm technologies requires major additions to the technology information developed for previous technologies. Synopsys?NanoChar characterization system is a complete, automated, characterization solution for standard cells and other macrocells that delivers the accuracy and capabilities required for 90-nm and below process geometries.Working in conjunction with Synopsys?highly-accurate HSPICE circuit simulator, NanoChar characterization system derives critical timing, power, and signal integrity data to create open, industry-standard Liberty (.lib) and Verilog (.v) files for use by all Synopsys tools as well as other EDA tools. The NanoChar characterization system lowers...

These errors are typically caused by a problem in the system environment setup. Check your version of System Generator by typing the following at the MATLAB command prompt:>> xlVersion Check your version of MATLAB by typing the following at the MATLAB command prompt:>> ver Check your version of the Xilinx ISE tools by typing the following at the MATLAB command prompt:>> system(\’xinfo\’)and go to the fileset.txt tab to confirm the version listed for each Xilinx tool. Next, make sure you have the latest service packs for all Xilinx tools and double-check that you are using compatible versions of all tools (including service packs and IP updates). See (Xilinx Answer 17966). Finally, check that the following environment variables are set as...

Synopsys Saberproduct:Synopsys Saber 2007.03 linux Lanaguage:english Platform:Winxp/Win7 Size:392MB

RTL (Front End) ToolsProduct DescriptionPlatform Express™, Mentor Graphics’ platform-based design product, enables design creation and verification by automating IP reuse. The product documents all aspects of IP using the IP-XACT™ XML databook format provided through The SPIRIT Consortium. The IP-XACT specification uses XML to create a machine-interpretable IP databook; it includes design information that software tools then use to automatically configure and integrate an IP block into a design. The power of IP-XACT is accessed through generators, which are programs that interpret the IP-XACT data to create design data. Platform Express comes with some of the most sophisticated generators available. These include mixed-language VHDL and Verilog generators that create ready-to-synthesize designs to work on a range of simulators, documentation generators,...

NanoSim™是一个针对模拟、数字和混合信号设计验证的大容量高性能晶体管级仿真器。它是一个稳定而简单易用的工具，为几百万门的片上系统设计提供了较高的仿真能力。对于0.13微米或更小工艺下的设计，它可以达到类似于SPICE的精度。 NanoSim结合了Timemill和PowerMill中最先进的仿真技术，在单独的一个工具里就可以同时完成时序和功耗分析。NanoSim与Timemill、PowerMill完全向下兼容，可以使用同样的网表和初始化设置，可以产生高精度高性能的结果。如果结合使用VCS，它可以在RTL级、门级、晶体管级等各个层次对设计进行仿真。 　　● 对于0.13微米或更小工艺下的设计它可以达到类似于SPICE的精度 　　● 仿真速度大大超过SPICE 　　● 可以仿真大容量的存储器和SOC设计　　● 为混合语言的片上系统设计提供了大量的工具 　　● 支持所有的SPICE网表和模型格式　　● 采用直观的、基于图形化用户界面的初始化配置和仿真环境，非常易于使用 　　● 提供大量内建的时序和功耗分析功能，提高了生产效率product:Synopsys NanoSim 2007.03.Linux Lanaguage:English Platform:/Linux Size:258MB

Synopsys Online Documentation——Synopsys的在线文档。 ::::::English Description:::::: SOLID E3-Dimensional Optical Lithography SimulationSOLID E is a window-based software package for simulating and modeling all the processes and techniques involved in optical microlithography. It is able to simulate the evolution of three-dimensional topographical features in integrated circuit devices throughout the various phases of the microlithography process. Due to its sound physical approach it has a high predictive power, enabling lithography engineers to draw on simulation results to optimize the process technology. This helps to increase the yield and to fully exploit the capabilities of existing equipment. SOLID E is the only lithography simulator on the market capable of simulating wafer topography in three dimensions. SOLID E with M-module – models photomasks and accurately predicts...

::::::English Description:::::: Synopsys’ Leda® 2007.03 is a programmable design and coding guideline checker that delivers full chip mixed-language (Verilog and VHDL) and mixed representation (RTL & gate) capabilities to speed development of complex system-on-chip (SoC) designs. Leda抯 pre-packaged rules greatly enhance a designer’s ability to check HDL code for synthesizability, simulatability, testability, reusability, and RTL/gate signoff. Leda detects clock synchronization-related bugs, isolates hard-to-time circuits, verifies layout considerations and improves DFT for higher ATPG coverage. Leda comes prepackaged with rules to improve performance of Synopsys tools, such as VCS MX, DC and Formality.   Key Benefits Finds complex bugs, such as those associated with multiple clock domains using static analysis Verifies consistency of design and SDC constraints for DC, PrimeTime and Astro...