EDA Design Page 200

ChipScope™ Pro tool inserts logic analyzer, bus analyzer, and virtual I/O low-profile software cores directly into your design, allowing you to view any internal signal or node, including embedded hard or soft processors. Signals are captured at or near operating system speed and brought out through the programming interface, freeing up pins for your design. Captured signals can then be analyzed through the included ChipScope Pro Logic Analyzer. The ChipScope Pro tool also interfaces with your Agilent bench test equipment through the ATC2 software core. This core synchronizes the ChipScope Pro tool to Agilent\’s FPGA Dynamic Probe scope option. This unique partnership between Xilinx and Agilent gives you deeper trace memory, faster clock speeds, more trigger options, all using fewer...

::::::English Description:::::: IC WorkBench (ICWB) is a powerful, hierarchical layout visualization and analysis tool with GDSII/OASIS viewing, layout editing, and high-speed lithography simulation and analysis. IC WorkBench is designed to address a variety of lithographic applications including: Mask Synthesis flow development, OPC model development and calibration, lithography verification error analysis,design rule creation and validation, yield and printability optimization of critical cells, and new process development.IC WorkBench provides qualitative and quantitative information on wafer imaging characteristicsunder varying parameter and process conditions. High Speed, High Capacity Viewing and EditingICWB builds on a solid foundation of fast GDSII/OASIS viewing and editing tool designed to handle the geometrically increasing file sizes of advanced process nodes. ICWB loads gigabytes of data in minutes and has...

::::::English Description:::::: Synopsys?TechXpress™ products enable a revolutionary amount of process insight in a minimum amount of silicon area that is not possible with conventional characterization technologies. A decade of experience in leading-edge technology development and yield optimization has shaped the TechXpress product line to enable the types and volumes of information that are required for successful nanometer-era technology development. Solutions Span Entire Semiconductor Process Life Cycle TechXpress solutions span the entire semiconductor process life cycle. Solutions are grouped into four chip sets that are used by process integration and yield engineers to target the specific tasks found at each stage of the process life cycle. The chips sets are classified as, ToolBox (for early materials and litho characterization), RaceTrack (for...

Synopsys公司发布的针对65nm 和 45nm 设计的电子类软件cadabra。   ::::::English Description:::::: Library developers are facing increasing challenges at the 65nm and 45nm nodes, including increasing design rule complexity, time-to-market pressures, library richness, and late design rule changes. Manual layout is becoming increasingly impractical and expensive. The Cadabra® product offers a fully automated tool for the creation of standard cells layouts from SPICE netlists, and for migration of existing standard cell layouts to new design rules or architectures. With easy to use graphical interfaces and results that rival hand-crafted, the Cadabra product is the market leader in automated standard cell layout. Design Rule ComplexityWith advanced manufacturing processes, the number of design rules that must be enforced for each layer is increasing rapidly. Moreover, many of the newer...

The National Instruments LabVIEW Execution Trace Toolkit gives real-time developers an interactive tool for analyzing and verifying NI LabVIEW Real-Time code execution. With minimal modifications to your embedded code, these tools graphically show multithreaded code execution while highlighting thread swaps, mutexes, and memory allocation. Using this information, you can optimize the real-time code for faster control loops and more deterministic performance. The toolkit allows you to verify code execution on LabVIEW Real-Time targets including PXI controllers, Compact FieldPoint controllers, FieldPoint controllers, compact vision systems, real-time PCI plug-in boards, and desktop PCs running the Venturcom Phar Lap ETS OS. The Execution Trace Toolkit requires Windows 2000/XP on the host machine. Interactively analyze and benchmark thread and VI execution Optimize performance by...

The Internet has opened many new opportunities and uses for personal computers and workstations across every industry and application area. Scientists and engineers are finding that important functions can be performed across the Internet, such as research, publishing conclusions, displaying data across the Web, archiving source code versions, and scheduling for test development teams. In addition to taking advantage of the Internet, virtual instruments are addressing remote or distributed applications more and more. Using the National Instruments LabVIEW Internet Developers Toolkit, you can easily incorporate a variety of electronic communications capabilities, such as XML, CGI, and FTP transfers into your virtual instrumentation applications. Read, write, and parse XML documents with a cross-platform DOM parser Send files or raw data to...

::::::English Description::::::The National Instruments LabVIEW Datalogging and Supervisory Control (DSC) Module is the best way to interactively develop your distributed monitoring and control systems. With the NI LabVIEW DSC Module, you can extend your LabVIEW application to view real-time and historical data, configure alarms and events, set up security on your applications, easily network OPC devices and LabVIEW Real-Time targets together into one complete system, and efficiently log data to the distributed historical database. The LabVIEW DSC Module features intuitive wizards and dialog boxes to help you develop applications faster and better. Built-in networking for data sharing and integrating third-party devices Networked database for distributed data logging Real-time and historical trending Graphical development for distributed monitoring and control User-level security...

The NI LabVIEW Embedded Module for ADI Blackfin Processors is a comprehensive graphical development environment for embedded design. Jointly created by Analog Devices and National Instruments, this module seamlessly integrates the NI LabVIEW development environment and ADI Blackfin embedded processors. With the LabVIEW Embedded Module for Blackfin Processors, you can take designs from concept to production in a single, integrated development environment by including all the tools you need to create your application quickly in LabVIEW and ultimately target custom-developed hardware. By using this approach, you can reduce development time and cost while delivering a high-performance embedded processing solution.Product:NI LabVIEW Embedded Development Module 2.5 Lanaguage:english Platform:Winxp/Win7 Size:315MB

Advanced Design System is the leading electronic design automation software for RF, microwave, and signal integrity applications. ADS pioneers the most innovative and commercially successful technologies, such as X-parameters* and 3D EM simulators, used by leading companies in the wireless communication & networking and aerospace & defense industries. For WiMAX™, LTE, multi-gigabit per second data links, radar, & satellite applications, ADS provides full, standards-based design and verification with Wireless Libraries and circuit-system-EM co-simulation in an integrated platform.Key Benefits of ADS * Complete, integrated set of fast, accurate and easy-to-use system, circuit & EM simulators enable first-pass design success in a complete desktop flow * Application-specific DesignGuides encapsulate years of expertise in an easy-to-use interfaceProduct:Agilent Advanced Design System ADS 2006A Linux...

在采用现有 IP核创建系统级芯片(SoC)时，关键是在设计周期之初，在目标环境中快速地配置和验证IP核。在采用多个IP模块和诸如AMBA的芯片级总线进行设计创建时，设计人员需要能够轻易地完成将多个IP模块连接到总线上并进行配置，从而能够将精力集中在设计中新的逻辑电路上。采用了DesignWare IP 重用工具，IP的创建者可以将自己的IP以某种格式进行打包，这种格式将引导IP集成者完成IP的配置、实现和验证。这样，IP集成者就可以用若干小时，而不是若干天的时间来创建复杂的IP模式和子系统，并开始对它们进行验证，从而大大缩短了整个设计周期。 　　Synopsys为单个IP模块和基于IP的子系统提供了一整套的IP工具，使得IP的创建者和集成者能够轻易地创建和支持复杂的IP。 　　● coreBuilder -将IP有效打包 　　● coreConsultant -引导用户完成IP核的配置和集成 　　● coreAssembler -帮助用户创新和管理打包的基于IP的子系统，包括装配、配置和实现 ::::::English Description:::::: The Synopsys family of coreTools is a comprehensive set of intellectual property (IP) packaging and integration tools for use in a knowledge-based design and verification flow. The tools enable designers to realize maximum productivity gains when using IP in their desing. By using an IP-based design and verification flow with IP packaged for assembly, the risk configuration, and subsystem integration errors is virtually eliminated, and designers have seen over a 60% reduction in SoC or platform design time and achieve the highest QoR in the implementation of the design.The coreTool family includes:coreBuilder™ – a robust packaging tool that allows designers to capture the knowledge...