EDA Design Page 204
The DesignWare Library provides a comprehensive portfolio of synthesizable and verification IP including an AMBA-based on-chip bus solution, memory IP, popular processor cores, bus and I/O standards, and performance enhancing datapath IP elements. The following product documentation is for the DesignWare Library\’s synthesizable and verification IP components. You can access product documentation for the DesignWare digital and mixed-signal IP cores using the “Search for IP” box in the upper right hand corner of this page.product:Synopsys DesignWare.vip Smartmodels 2005.09 Lanaguage:english Platform:Winxp/Win7 Size:101MB
Seamless為MentorGraphic提供的硬體/軟體協同驗證工具，提供高效能和高準確性的軟硬體虛擬平台混合驗證，能降低整合性錯誤的風險並加快產品上市的速度，seamless支擁有業界最大的協同驗證模型資料庫，包括嵌入式設計最常使用的所有架構，而每個 Seamless處理器模組包含一個指令集模擬器，能夠執行組合語言碼和除錯,並提供處理器中的暫存器叢集所有的控制和觀察， Seamless 並有記憶體最佳化技術的專利，這個技術在嵌入式軟體的執行上提供速度上的提昇，並使邏輯模擬器有詳細分析和除錯的功能，配合這些特性 Seamless 可將單晶片系統的測試從硬體雛型系統轉換到虛擬的雛型系統，因此可輕易的更改軟硬體模組，在投入硬體前就能確保軟硬體介面的準確性，大幅的縮短了設計的時程。 Seamless CVE是Mentor Graphics推出的嵌入式系统软/硬件协同验证解决方案。通常，嵌入式软件的开发会滞后于硬件开发，特别是软/硬件的集成调试，必须等到物理原型生产出来以后。所以无法在设计的早期发现软/硬件接口之间的问题。一旦硬件原型有错，修改后还必须从新生产，然后再进行调试。整个设计过程排错困难，周期长，投入高。Seamless CVE将嵌入式软件开发工具和逻辑仿真器结合起来，使项目开发小组在物理原型（电路板或芯片）生产出来之前，就能够使用同一个系统模型进行高性能的软/硬件协同验证，使软件和硬件开发成为并行的过程，从而及早发现并改正软/硬件接口中的错误，缩短设计周期，减少投入。Seamless CVE还可以按照用户的配置来运行，使设计人员既能在需要时观测到所有的软/硬件交互细节，也能通过不同的优化策略来加速软件代码的执行，提高协同验证的效率。 主要特点： → 缩短嵌入式系统（板上系统和片上系统）的开发周期。 → 减少硬件原型的设计反复次数。 → 加速设备驱动程序和硬件诊断程序的调试。 → 无须更改软/硬件设计。 → 拥有专利的一致性存储器服务器和动态优化技术能够提供最佳的协同验证性能。 → 支持业界主要的微处理器和控制器模型。 → 接口开放，能够集成第三方的设计和验证工具。product:Mentor Graphics Seamless Lanaguage:english Platform:Winxp/Win7 Size:1.27G
Verification of ESD structures and other protection circuits is often a time consuming and tedious task. How do you do it? Complex DRC rules? An assortment of specialized rule decks? Home-brew tools? Recently a colleague and I published a paper which used one of the Mentor tools (Calibre® PERC) to help with this ESD checking. If you’re interested, the paper is available on-line here: New Flow for Automating Verification of ESD Design Ruleshttp://www.soccentral.com/results.asp?EntryID=29425 Also of interest is the ESDA Symposium in the Los Angeles area (Anaheim to be precise) over the coming week. I’d encourage you to pop in if you can. Last year’s event was our first at the ESDA Symposium, and it was very good. Lots of great...
Dramatically Reduces ASIC Verification Time Compares two designs – RTL to gate for synthesis and ECOs – Gate to gate for layout spins – RTL to RTL for language conversion Highest capacity tool – Verifies multi-million gate ASIC ’s as one Fastest route to correct design – Exact location of errors – Tests fixes within the verification session Where to Use FormalPro : FormalPro is a Regression Testing Tool That verifies all stages of gate-level implementation of a design From synthesis through to tape out Benefits GUI for design entry and initial debug Command line mode for regression testing Constraint language and TCL scripting Incremental Verification Recompile only design that has changed Restart at intermediate pointsproduct:Mentor Graphics FormalPro 2006.1_1-3 Linux...
Synopsys, Inc. (Nasdaq:SNPS), a world leader in semiconductor design software, announced the availability of advanced device parameter measurement functionality in its Hercules(TM) Physical Verification Suite (PVS). Developed to support the latest release of 65-nanometer (nm) design kits from IBM (NYSE: IBM), this new functionality enables IBM foundry customers using the Hercules layout versus schematic (LVS) rule files in the kit to easily and accurately correlate device behavior to the IBM process. These IBM foundry customers also have access to the latest Hercules design rule checking (DRC) as part of the 65 nm design kit release. These files are qualified for accuracy and optimized for performance. “We have been supporting Synopsys Hercules PVS for over a decade,” said Dave Harame, director...
DiscoveryTM Pioneer-NTB是一套功能全面的SystemVerilog测试平台自动化工具，可与流行的VHDL和Verilog仿真器配合使用。Pioneer-NTB能够让工程师在混合仿真环境中方便地应用先进的基于开放标准的验证方法。Pioneer-NTB是在Synopsys® VCS®全面RTL验证解决方案中各项功能强大并经产业证实的技术以及Vera®测试平台自动化工具的基础上开发而成，提供了即时获得由VCS和Vera构成的广泛的体系的能力。Pioneer-NTB还支持OpenVera®语言，能够让现有Vera验证环境容易地移植到Pioneer-NTB上，并可实现高达2倍的验证运行时间性能提升。[img]http://www.synopsys.com.cn/synopsys/products/images/Discovery-009.gif[/img]主要优势 ● 支持SystemVerilog验证功能，从而可以采用基于面向对象、先进的数据类型、约束随即激励、功能覆盖以及断言等技术来创建高效的测试平台环境。 ● 支持Synopsys的参考验证方法学（RVM），并包括了基本模块库，从而加快了按照业界最优做法来实现覆盖率驱动、约束随机和基于断言验证等技术的鲁棒且可重用的验证环境的开发过程。 ● 内置、完整地支持了SystemVerilog断言（SVA），并且拥有一个包括50多个可用的检查器库，以及一个包括多种流行接口协议标准的断言IP库，从而可以实现基于断言的可验证设计（DFV）方法的快速投入应用，加快设计错误检测的速度，改善设计方案质量 ● 内置功能和断言覆盖率以及统一的覆盖率报告功能，对验证目标的达成度提供综合全面的观察 ● 本征、快速地支持高质量验证IP的VCS验证库，能够加快大范围采用了标准接口协议的设计的先进验证环境的开发和执行速度。 ● 对于OpenVera语言的深入支持，让Vera语言使用者能够很容易地将现有的验证环境移植到Pioneer-NTB上，并实现高达2倍的性能。product:Synopsys Pioneer-NTB SystemVerilog Testbench 2006.06 Linux Lanaguage:English Platform:/Linux Size:319MB
一款在HDL.Designer.SeriesHDL.Designer.Series软件中使用FPGA/PLD/HDL设计工具。product:Mentor Graphics DesignAnalyst 2005.1 FPGA/PLD/HDL设计 Lanaguage:English Platform:/WinNT/2000/XP Size:28MB
在将具有竞争性、不同凡响的产品推向市场的设计过程中，可测性设计日益变得重要起来。从没有“放之四海皆准”的测试方案，这就是为什么Mentor Graphics推出广泛的DFT工具的原因。这些世界领先的工具缩短了设计开发时间，并保证更高质量。所有这些都比现在其它任何DFT工具的风险小。我们的DFT服务队伍会帮助你轻松地进行测试点插入，测试矢量生成和故障仿真，保证在你的设计限制范围内达到最高的测试覆盖率。 Comprehensive DFT Solution for SOC Designs DFT process in ASIC design flow DFT(Design-For-Test)是Mentor Graphics公司的黄金产品，该产品在近三年来一直独居技术、市场世界第一。该产品之所以具有如此的地位，关键在于以下两方面: ASIC设计师公认测试、综合在ASIC设计中同等重要；Mentor Graphics有着高水平研发队伍，总能使自己超前发展。如图所示为一个完整的测试解决方案，这样的解决方案包含边界扫描设计(Boardary Scan)，内部全扫描(Full Scan)或部分扫描设计(Partial Scan)，自动测试向量生成(ATPG)，存储器内建自测试(Memory BIST)，以及逻辑内建自测试(Logic BIST)的设计技术。测试是非常复杂的问题，Mentor Graphics公司主张不同类型的测试问题，应选用不同的工具去解决。这样方能保证精确有效的测试结果。 [img]http://cn.sun.com/isv/solutions/images/mentor-2_01.gif[/img] [img]http://cn.sun.com/isv/solutions/images/mentor-2_02.gif[/img] 确保设计能于制造后正确工作 DFT工具为设计的可测性增加了设计电路（RTL或者gate level） DFT工具为投入生产的设计生成测试组来检测其缺陷 基于DFT结果进行失效分析 [img]http://www.mentorg.com.cn/images/products/test_Insert.gif[/img]product:Mentor Graphics Design-For-Test(DFT) 2006.3.10 可测性设计 Lanaguage:English Platform:/Linux Size:197MB
>::::::English Description:::::: Raphael is the gold standard, 2D and 3D resistance, capacitance, and inductance extraction tool for optimizing multi-level interconnect structures and on-chip parasitics in small cells. As a reference field solver, Raphael provides the most accurate parasitic models in the industry. Trusted by major foundries, interconnect parasitics generated by Raphael are included as part of their design reference guide. Benefits Analyze complex on-chip interconnect structures and the influence of process variation Create a parasitic database for both foundries and designers to study the effect of design rule change Generate accurate capacitance rules for layout parameter extraction (LPE) tools product:Synopsys Raphael 2006.12 Linux Lanaguage:english Platform:Winxp/Win7 Size:36MB
FEATURED TECHNOLOGY CustomSim Circuit SimulationUnified AMS verification technologies deliver 4x performance improvement VCS Multicore Technology2x verification speed-up on complex designs Lynx Design SystemThe Lynx Design System is a highly automated, production-ready, chip implementation platform. Power-Aware TestBreakthrough technology in DFT MAX compression and TetraMAX ATPG. SuperSpeed USB 3.0Learn about USB 2.0 vs. 3.0 and how to evaluate a USB IP solution.product:Synopsys Circuit Explorer 2006.03 Linux Lanaguage:english Platform:Winxp/Win7 Size:62MB