EDA Design Page 179

OverviewWith process geometries reaching90-nanometers (nm) and below, thereare many nanometer effects that canimpact timing. Accurate analysis ofthese effects is required to identify realtiming issues.Synopsys’ NanoTime tool is thenext-generation transistor-levelstatic timing analysis solution thataddresses the emerging challengesin signal integrity (SI) analysisassociated with custom designs.NanoTime offers concurrent timingand SI analysis, accuracy withinfive percent of HSPICE®, and theperformance required to analyzecomplex transistor circuits overnight.Its seamless integration with Synopsys’PrimeTime® product enables full-chipanalysis of designs that includes bothgate- and transistor-level blocks.NanoTime is a key component of theSynopsys custom design verificationsolution that includes CustomSim®and HSPICE for circuit simulationand ESP-CV for symbolic simulation.product:Synopsys Nanotime 2007.12 SP2 Linux Lanaguage:english Platform:Winxp/Win7 Size:81MB

The Milkyway™ Database provides the unifying design storage for Synopsys’ Galaxy™ Design Platform. The production-proven, widely used Milkyway database provides persistent data storage that links Galaxy platform tools together thereby eliminating the need for large, intermediate exchange files and preventing design intent loss through mismatched syntax of exchange formats. Milkyway is proven on well over 10,000 tape-outs including the latest 90 and 65 nanometer technology designs. Designed to be extensible, Milkyway is continuously augmented with new capabilities such as those required for signal integrity, power reduction, and yield enhancement. The Milkyway database C-API was opened for customer interfacing in 1998 and is available to 3rd parties at no charge through Synopsys\’ MAP-in program. Key Features and Benefits * Production-proven database...

IC-CAP 2008 (with Add-ons 1 & 2): Bringing Innovative Modeling Technology to Our Customers The IC-CAP 2008 release introduced the IC-CAP Target Modeling Package. Used to extract MOS models from semiconductor manufacturing process targets, the Target Modeling Package enables designers the to develop device simulation models earlier in the design cycle for faster overall integrated circuit design. The IC-CAP 2008 Add-On 1 release introduced the Hisim2.4 Model Extraction Package, an easy-to-use and efficient flow to measure and extract DC and RF parameters of the Hisim2.4.1 model. The IC-CAP 2008 Add-On 2 release introduced a similar extraction package for the Hisim_HV model for symmetrical HVMOS and asymmetrical LDMOS devices. New with this Release * Target Modeling Package * HiSIM2.4 Model Extraction...

Calibre® is the overwhelming market share leader and the industry standard for IC physical verification, due to the outstanding performance, accuracy and reliability of Calibre products. Over the last two years, Calibre nmDRC™ has reduced average DRC runtime by a factor of five, while Calibre\’s innovative Hyperscaling and MTFlex™ technologies have cut memory requirements in half. Calibre nmDRC also reduced overall cycle time with incremental DRC, which allows designers to make DRC runs in parallel. As DRC violations are reported, designers can immediately fix and recheck just the affected areas, while the initial DRC run continues. To handle complex and multi-variate, multi-dimensional checks that are not adequately addressed by traditional design rules, Calibre nmDRC\’s equation-based DRC (eqDRC) capability enables designers...

SymXpertTM is a powerful symbol creation tool that automates the symbol creation process by eliminating manual data entry, simplifying pin data validation, and standardizing symbol generation through the use of ECAD-neutral templates. SymXpert\’s intelligent content extraction technology speeds up the symbol creation process by a factor of 8 – 24 times, reduces design bottlenecks, eliminates opportunities for errors that can cause downstream manufacturing problems, and frees up design resources for more critical design tasks. As large-pin-count components are more frequently used in PCB designs, the creation of schematic symbols for new parts has become increasingly time consuming and error prone. Data for hundreds or even thousands of pins must be manually entered into a schematic capture program, painstakingly checked for...

Mentor Graphics AMS 2008.1 （Mentor Graphics® 模拟/ 混合信号(AMS) 集成电路设计ADVance MS （AMS）包含有Mentor三种仿真内核，Eldo，ModelSim，和 Mach TA，支持数模混合电路各个不同阶段的仿真工作，从RTL，Gate-Level，到 transistor level。支持的语言包括有 VHDL, Verilog，VHDL-AMS，Verilog-A，SPICE 和 C。ADVance MS单一核心的解决方案和最佳化的技巧，可以提供数百万门的混合讯号线路和单一系统化晶片快速且准确的仿真。 Mentor Graphics加强ADVance MS混合讯号功能验证平台的延展性 Mentor Graphics加强ADVance MS混合讯号功能验证平台的延展性 明导国际 (Mentor Graphics) 于8月宣布开始供应ADVance MS™ (AMS) 2008版，这套工具新增加对于SystemVerilog和SystemC语言的支援，使其市场地位再度加强，成为目前最具延展性的混合讯号功能验证平台。AMS 2008还提供更强大的工具能力，工程师无论在数位为主 (digital-centric) 或是类比为主 (analog-centric) 的设计流程中，都能验证他们的设计，确认其功能符合原始规格。 AMS 2008版现能为八种语言提供完整支援，包括SystemVerilog、SystemC、VHDL、Verilog、SPICE、VHDL-AMS、Verilog-AMS以及C语言，让使用者能在单一模拟环境中，执行从系统规格阶段到后布局验证阶段的功能方块层级检查及全晶片功能验证。 Mentor透过AMS 2008提供一个共同平台，以便扩大数位验证和类比验证，支援混合讯号设计。它能支援数位为主的验证，例如测试平台 (testbench)，包括定向测试 (directed testing) 和准随机测试；它能支援类比为主的验证，例如电路模拟，包括直流、交流、暂态、参数、Monte Carlo以及边界条件 (Corner)；它还可以支援混合讯号为主的验证，例如「棋盘式」(checkerboard) 分析。利用这个共同验证平台，AMS 2008可以针对类比与混合讯号系统单晶片设计，同时执行由上而下的设计和由下而上的验证。 AMS 2008也整合Verisity SpecMan Elite，使得新型混合讯号设计所需的复杂验证策略更容易实行；这项整合让设计人员可以更早验证他们的架构或功能分割，并在整个设计流程中，做为测试平台而不断重复使用。这些优点让工程师更早而且更容易的找出及更正基本设计中的各种问题。 对于设计团队分散于世界各地的跨国企业，AMS让每个团队都能以他们喜欢的语言执行功能方块层级验证；当功能方块结合在一起，成为完整的全晶片实作，甚至其中可能包含其它厂商的矽智财时，AMS就也用来执行最终的全晶片验证，并将设计中各个组件以原来语言保留，降低资料相容性及完整性发生错误的风险，找出使用多种验证工具所带来的功能性缺陷。AMS还能与任何设计流程整合，进而提供无比的弹性，不受现有工具的牵绊。 Mentor Graphics深次微米部门副总裁暨总经理陈志贤 (Jue-Hsien Chern) 表示，ADVance MS是具有原创性的多语言、多层级模拟工具，可支援类比、混合讯号及类比设计。我们拥有多年的技术研究和客户合作经验，并以它们做为此平台的发展基础；在增加对于SystemVerilog和SystemC语言的支援后，Mentor进一步扩大它在可延展性验证解决方案供应方面的领导地位。 Mentor Graphics ADVance MS模拟技术Mentor Graphics ADVance MS (AMS) 工具是语言中立的单核心功能验证环境，可同时支援数位、类比、混合讯号和射频电路。此平台是以四种高效能、已通过客户考验的模拟技术为基础：用于类比的Eldo™、用于数位的ModelSim®、用于电晶体层级的Mach以及用于射频模拟的Eldo RF。AMS平台推出已有五年，是一套非常成熟的功能验证环境，目前已用于一百多个客户地点。 product:Mentor Graphics AMS 2008.1 Win Lanaguage:English Platform:/win2000/winxp Size:227MB

Synplicity’s Synplify Premier Linux software is the ultimate FPGA timing closure and debug solution. It builds upon Synplicity’s industry-leading synthesis technology by adding graph-based physical synthesis and real-time simulator-like visibility into operating FPGA devices. The Synplify Premier tool’s graph-based physical synthesis technology addresses timing closure by merging optimization, placement, routing and generates a fully placed and physically optimized design ready for final routing using the FPGA vendor routing tool. The highly accurate correlation between the Synplify Premier product’s timing estimates and final design timing enables more aggressive optimization resulting in improved device performance. In addition, the Synplify Premier product offers FPGA Designers and ASIC Prototypers the most efficient method of in-system verification of FPGAs. The Synplify Premier software dramatically accelerates...

FPGA Design \”Made easy\”Active-HDL™ is a Windows® based integrated FPGA Design and Simulation solution. Active-HDL includes a full HDL graphical design tool suite and RTL/gate-level mixed-language Simulator. The design flow manager evokes 80 plus EDA and FPGA tools, during design, simulation, synthesis and implementation flows, making it a seamless and flexible design and verification platform. Active-HDL supports industry leading FPGA devices, from Actel™, Altera®, Lattice®, Quicklogic®, Xilinx® and more. Top Features * Multi-FPGA & EDA Tool Design Flow Manager * Graphical Design entry & editing * Code2Graphics and Graphics2Code * Import/Export Legacy Designs * Pre-compiled FPGA vendor libraries * High Performance Mixed-Language RTL Simulator * IEEE Language Support: VHDL, Verilog®, SystemVerilog Design, SystemC * Automatic Testbench Generation * Advanced Debugging...

Encounter RTL Compiler allows engineers to look across the entire design as they employ concurrent optimization techniques, such as making tradeoffs among timing, area, and poweTo maximize performance, decrease die size, reduce power consumption, and boost productivity, designers need a global synthesis solution that enables concurrent optimization of timing, area, and power. Encounter RTL Compiler, a key component of the Cadence Logic Design Team Solution, delivers production-proven global synthesis for faster, smaller, and low-power chips in less time. With its unique set of patented global-focus algorithms, combined with new physically-aware optimization and analysis, Encounter RTL Compiler cuts design time while ensuring the highest quality of silicon. Features/Benefits * A well-balanced logic structure isolates critical paths and reduces power, area, and...

attice Announces ispLEVER 7.1 Service Pack 1 FPGA Design Tool Suite Tool Suite Includes New 3rd Party Synthesis and Simulator Versions, Integrated ORCAstra Utility and Concurrent LatticeMico32 Release HILLSBORO, OR – SEPTEMBER 8, 2008 – Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of Service Pack 1 for Version 7.1 of its ispLEVER® FPGA Design Tool Suite. The release integrates Lattice\’s ORCAstra configuration design utility, features Reveal™ Logic Analyzer support on the Linux Operating System, adds new versions of Synopsys\’ Synplify® Pro synthesis and Aldec\’s Active-HDL™ Lattice Edition simulator, includes support for automotive temperature grade LatticeXP2™ FPGAs and provides the latest LatticeMico32™ embedded open source microprocessor enhancements. \”This ispLEVER service pack adds a wide range of new utilities...