EDA Design Page 175

Timing closure in today advanced designs remains the number one challenge for designers today, especially at 90-nanometers (nm) and below. A trusted timing sign-off solution that accurately models and predicts silicon behavior is required to enable designers to quickly achieve timing closure. The Synopsys PrimeTime static timing analysis solution is the most trusted and advanced timing sign-off solution for gate-level designs. It is the industry de-facto gold standard for gate-level static timing analysis and is a key component of the Galaxy?Design Platform. With a wide breadth of sign-off analysis capabilities, the PrimeTime STA solution provides a comprehensive and unmatched environment for timing sign-off and serves as an industry yardstick for timing analysis and sign-off. It delivers to designers extensive timing...

::::::English Description:::::: Micro-Cap 9 is an integrated schematic editor and mixed analog/digital simulator that provides an interactive sketch and simulate environment for electronics engineers. Since its original release in 1982, Micro-Cap has been steadily expanded and improved. Micro-Cap 9, the eighth generation, blends a modern, intuitive interface with robust numerical algorithms to produce unparalleled levels of simulation power and ease of use. Nothing else comes close. Faster Algorithmic improvements, optimized code, and an integrated, seamless, analog/digital simulation interface contribute to the stunning speed of Micro-Cap 9.   More powerful Numerous features contribute to Micro-Cap 9 s power. Among them are:   Integrated schematic editor and simulator. Interactive editing and simulation Native digital simulator Transient analysis AC analysis – for investigating...

High-Level Algorithm Implementation for FPGAs and ASICs The Synplify DSP tool provides a unique high-level synthesis methodology that realizes significant productivity and portability advantages. System and algorithm designers can quickly capture complex algorithmic behavior using the Synplify DSP library. The Synplify DSP synthesis engine allows designers to automatically implement and explore area/speed optimized RTL implementations from a single model. This eliminates the burden of hand-coding functions and architectural optimizations and results in significantly faster design capture, speeds time-to-market, and enables rapid design exploration for improved quality and lower cost.product:Synopsys Synthesis Tools 2008.09 SP2 AMD64 Lanaguage:english Platform:Winxp/Win7 Size:277MB

* Rapidly create and verify technology independent DSP models that are fully portable across vendor and device technologies. * Unique Synplify DSP synthesis engine automatically creates optimized algorithm RTL architectures from your DSP model. * Powerful DSP synthesis optimizations enable exploration of speed/area/device technology tradeoffs without changing your DSP model or verification. * Comprehensive DSP library with full multi-rate support and advanced fixed-pint quantization analysis. * M-Control feature enables use of M-language for concise expression of complex state machine and control logic functionality. * Vector support enables concise expression of parallel and multi-channel algorithms common in wireless and video applications.product:Synopsys Synthesis Tools 2008.09 SP2 Linux Lanaguage:english Platform:Winxp/Win7 Size:268MB

Lattice Semiconductor (NASDAQ: LSCC) today announced Version 7.2 of its ispLEVER® FPGA design tool suite with advanced place and route algorithms that deliver higher performance results in as much as 30% less time. The ispLEVER 7.2 software also now supports Lattice\’s clock boosting flow for the LatticeECP2™ and LatticeECP2M™ FPGA families. Clock boosting can result in up to a 5% increase in FMax with no additional user input. In addition to performance improvements, ispLEVER Version 7.2 continues to improve designers\’ productivity with additional control, analysis and workflow enhancements, and includes the latest release of Synopsys\’ Synplify Pro® advanced FPGA synthesis solution. “Our ispLEVER design tools continue to evolve in order to satisfy the needs of FPGA designers,” said Mike Kendrick,...

Sisoft Quantum-Sl 2007.08 SP4 provides a truly integrated solution for signal integrity and timing analysis of complex high-speed multi-board systems.   Quantum-SI implements a methodology that encompasses pre-layout and post-layout simulations with rigorous waveform processing, automatically extracting waveform quality reports and interconnect delays. Extracted interconnect delays are utilized by static timing analysis for both synchronous and source-synchronous designs. Quantum-SI provides the flexibility to perform all signal integrity and timing analysis at either the core of the chip, the pad of the I/O, or the pin of the package of both the source and target components. Product:Sisoft Quantum-Sl 2007.08 SP4 Lanaguage:English Platform:/win2000/winxp Size:165MB

::::::English Description:::::: Filter Solutions contains many different types of filters to choose from. Passive, Transmission Line, Active, and Digital IIR and FIR are all supported. See our FIR page for information about our FIR filters that are supported. Analog and IIR filters may all be quickly and easily delay equalized with our real time updates to all pass pole/zero manipulation. Passive and active filters may be quickly and easily modified and reanalyzed with our real time analysis feature. Finite Q may be included in the analysis. Digital filters may be modified and analysis in real time for finite precision analysis. Table one below lists the type of analog filters that are supported along with the parameters that are available for...

LinkCAD 5.7为AutoCAD DXF, Gerber RS274X, Calma GDS-II, CIF, PostScript, IE3D, TLC等等文件做的转换工具。Product:LinkCAD 5.7 Lanaguage:English Platform:/win2000/winxp Size:11MB

Altium发布了其新一代电子设计解决方案Altium Designer的最新版本Winter 09。Altium持续在市场上推出一系列设计新概念和新技术，开发先进技术，帮助电子产品设计人员更快更好地将设计转化为产品。 在最新版本Winter 09中，原来已有的三维PCB设计功能被提升到了一个更高速的新境界。新功能可以让工程师管理从产品设计到制造的过程转换，尝试新的设计技术并得以深度挖掘可编程器件的潜力。新增加的应用控制面板帮助工程师解决了FPGA测试上的难题，并可以远程监控FPGA内的设计。新的即插即用型软件平台搭建器让系统的整合更容易，同时提供在可编程器件的“软”硬件环境里的一系列标准服务以供使用。 三维PCB可视引擎性能大提升 – 更加准确和快速 以前版本里已经提供的Altium三维PCB可视设计环境可以让工程师在设计的同时实时观看PCB设计的三维外观。通过可视环境，工程师可以直接将机械CAD信息反应在PCB设计上，帮助在元件的放置和距离上做出最优选择。 Winter 09版本优化了内存并将三维PCB可视化系统的速度提升至最高达7倍之多。 其他方面性能的提升还包括：二维制图－速度提升3倍；二维透视－性能提升11倍；高亮和对比度调试－性能提升9倍，三维旋转－性能提升5倍。 Winter 09版本还提供了一系列目前已有的显卡的性能对比供用户参考，更好地保护用户的投资，为软件的投入提供最大的回报。这使设计人员能够更好地利用现有的计算硬件。 优化三维PCB图形引擎至关重要，由此可以极大的提高整个软件的性能，并降低对硬件的要求，使得系统的反应速度更快，把图形延迟对设计造成的影响变得最小。 增强PCB建模功能 － 真实表面处理和其他可视化功能增强 Altium在最新的版本里扩充了其实时三维PCB设计功能。最新的版本支持三维建模的纹理映射，使设计师能过对设计板和元件进行表面处理。 Altium提供增强的过孔功能，并允许在不同信号层上使用不同尺寸的焊盘。过孔的叠加可以支持更高的跟踪密度。工程师还可以通过元件焊盘来实现过孔的偏移。 所有上述的增强型功能都提高了PCB设计的精确性，并为设计板布线和可视化提供了新的设计思路。 新的交互式布线功能 － 高速绕过走线和环绕功能 Altium同时将其5月推出的交互式布线功能推向一个新的层次。新的布线引擎对差分对信号和总线的布线（多重布线，和追踪）进行了增强。新的布线引擎支持对当前路径物件的绕过，对现有布线进行环绕并生成新的路径，对路径物件（包括过孔）的推挤，和对布线路径的智能完成。新的引擎同时也保证了布线的速度和流畅性。 这样，工程师可以在交互式布线的同时实现差分对和单闭端的管脚交换。这在FPGA器件设计的时候十分有用，因为在很多时候管脚会发生某种特殊的信号。Altium同时还通过交互式的布线引擎来自动解决布线中遇到障碍需要改变各种路径的各种情况。 设计新概念 － 设计管理延伸到制造管理 Altium还新推出一项技术用于帮助工程师更好的管理从设计到制造的流程。 当工程师准备将设计付诸实际生产时，通常会为制造环节的不同人群提供大量各类文件。通常信息主要来源于：原理图，PCB文件，原料清单，元件数据，FPGA和软件的源码及目标文件，以及设计流程报告等。对于同样的文件，有些使用者需要打印，而有些则只需要相应的PDF文档。所以生成正确的文件是一项费时费力的工作，而且随时都有没有及时更新或者发生错误的可能，这在时间和成本方面都有可能代价高昂。 Altium Designer 的这一新版本增强了对所有设计文件的版本控制。Altium采用新的技术在设计环境中创建并跟踪文件的更新记录。通过集中管理输出文件的定义和产生过程，整个输出的流程更简单顺畅了。所有的文件都可以轻易生成为各种形式，大部分是智能PDF和在线的格式。 该功能和三维的PCB设计环境相链接，工程师可以借此在生成生产文件之前很直观地检测他们的设计，避免不必要的错误。 新的设计发布管理功能的向导式界面可以管理设计发布的整个流程，并可以使之向设计团队之外的相关人员开放。通过中央控制面板可以生成各类输出文件，并发送到相关人员。设计发布管理功能还可以对设计进行“快照”，便于设计师进行收回，修改和重新发布，并对所有相对应支持文件进行正确性的检查。该功能可实现设计的多次发布，并提供完整的发布历史以供追溯。 在PCB布线阶段，Altium Designer新版本加入了针对制造的设计规则以尽量避免在生产阶段可能会出现问题。工程师得以在设计阶段就可以实时进行一系列问题的检查，避免了后期不必要的返工，可以更快速的把产品推向市场。 应用控制面板 － 测试FPGA的新工具 Altium在新版本里推出了应用控制面板，以帮助解决FPGA设计中的一些问题，并可以远程的监测可编程器件内部的设计。 Altium的LiveDesign原理让工程师可以把FPGA的设计视为整个设计中一部分。新工具可以让工程师更好的模拟和探索可编程器件内部的设计。 应用控制面板不需要Altium Designer的完全许可证就可以下载并安装，并使面板和FPGA设计进行交互，使用户能够调试或者甚至在产品发布以后增加新的功能。 即插即用软件平台搭建器 － 创建软设计中基本软件平台的新方法 Altium还在Altium Designer新版本中提出了即插即用的软件平台搭建器的概念。 通过Altium NanoBoard可重构硬件平台，工程师可以很容易地“整合”出硬件平台上所需的软件服务。这包括了电子设计中常见的设计元素：例如外设，通信模块，和支持正常工作所需要的各种驱动规则（由NanoBoard提供）。这样，基本但是必要的软件模块设计被简化成拖放预先配置软件模块到设计中，工程师得到了解放，能够真正地专注于核心的产品智能设计。软件平台搭建器提供一系列的驱动和软件规则来支持通过NanoBoard设计平台运行的外设。 供货情况 Altium Designer的最新版本Winter 09已经正式发布。Product:Altium Designer Winter 09 build 8.0.0.15895 Lanaguage:English Platform:/win2000/winxp Size:1.13G

What\’s New in Cadence Allegro 16.0 Platform What’s New in Cadence OrCAD 16.0 ProductsA flexible and scalable solution that adapts to your needs To stay competitive in today\’s market, engineers must take a design from engineering through manufacturing with shorter design cycles and faster time to market. To be successful, you need a set of powerful, intuitive, and integrated tools that work seamlessly from start to finish. Cadence® OrCAD® personal productivity tools (including Cadence PSpice®) have a long history of addressing these demands. Designed to boost productivity for smaller design teams and individual PCB designers, OrCAD PCB design suites grow with your needs and technology challenges. The powerful, tightly integrated PCB design suites include design capture, librarian tools, a PCB...