EDA Design Page 173

Sentaurus Process is an advanced 1D, 2D, and 3D process simulator for developing and optimizing silicon and compound semiconductor process technologies. Created by combining the best-in-class features from Synopsys and former ISE TCAD products, together with a wide range of new features and capabilities, Sentaurus Process is a new-generation process simulator for addressing the challenges found in current and future process technologies. Equipped with a set of advanced process models, which include default parameters calibrated with data from equipment vendors, Sentaurus Process provides a predictive framework for simulating a broad range of technologies from nanoscale CMOS to large-scale high-voltage power devices. Sentaurus Process is part of the comprehensive Synopsys suite of core TCAD products for multidimensional process, device, and system...

AUCOPLAN integrates data and documents from electrical and electro-mechanical engineering, automation technology, and process engineering planning.AUCOPLAN is characterized by maximum flexibility and adaptability to special labeling instructions, engineering processes and documentation regulations.AUCOPLAN can be obtained internationally through AUCOTEC\’s Global Partner Network, conforms to internationalstandards and is available in various language versions. AUCOPLAN supports current trends and technologies such as multi-user and client/server environments, database-driven engineering and object oriented modular design. AUCOPLAN has found its place among the market leaders of integrated I&E planning systems and has numerous references from its worldwide network, which includes leading companies of industrial sectors using DIN or ISA standard documentationProduct:Aucotec ELCAD Aucoplan 7.5 Lanaguage:english Platform:Winxp/Win7 Size:257MB

Foundry giant Taiwan Semiconductor Manufacturing Co. said today that it was engaging intellectual property player Virage Logic Corp. to develop libraries in support of early users of TSMC\’s 65nm technology. The agreement provides chip designers with memory compilers for SoC designs, the foundry said. It announced plans for 65nm production earlier this year. At every new technology node, the amount of chip space taken by on-chip memory increases dramatically, Edward Wan, senior director of design service marketing for TSMC, said in a statement. At the 65nm node, on-chip memory may occupy more space than logic or any other IP and therefore it\’s important for our customers to get early access to advanced memory compilers. Virage Logic is both a provider...

Designers increasingly use advanced multi-clocking architectures to meet the high-performance and low-power requirements of their chips. The 0-In® CDC verification solution focuses on the interaction between these clock domains. In fact, it addresses a number of critical verification issues that simply cannot be dealt with by simulation-based verification techniques. An RTL or gate-level simulation of a design (that has multiple clock domains) does not accurately capture the timing related to the transfer of data between clock domains. As a consequence, simulation does not accurately predict silicon behavior, and critical bugs may escape the verification process. The 0-In CDC verification solution rectifies this problem. The 0-In CDC verification solution sets the industry benchmark by providing the three essential elements for a...

  Mentor Graphics Design for Test v8 2009.1 Linux 确保设计能于制造后正确工作 DFT工具为设计的可测性增加了设计电路（RTL或者gate level） DFT工具为投入生产的设计生成测试组来检测其缺陷 基于DFT结果进行失效分析 product:Mentor Graphics Design for Test v8 2009.1 Linux Lanaguage:English Platform:/Linux Size:278MB

Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today announced that Cypress Semiconductor Corp. has successfully taped out its West Bridge™ Antioch™ peripheral controller multimedia 3G/3.5G mobile phone integrated circuit (IC) using the Synopsys Galaxy™ design platform RTL-to- GDSII low-power solution, including the PrimeRail dynamic power network analysis solution. The multithreshold CMOS (MTCMOS) power gating feature in the Galaxy design platform enabled Cypress to complete its ultra-low-power design with world-class performance and optimized standby current. PrimeRail, a key component of the Galaxy design platform, enabled peak current analysis for the multiple power domains of the Power Gating-based design during physical implementation. \”For our mobile phone chip design, we needed a solution that could address peak current problems...

FineSim Pro defines a new paradigm in full-chip circuit-level simulation, enabling the simulation of the most challenging analog/mixed-signal SoCs with SPICE accuracy and unprecedented performance. Diagram * Combination of accuracy and performance in a single executable allows large, mixed-signal designs to be simulated with very accurate SPICE and fast-SPICE solving techniques. This provides complete control of speed- versus-accuracy tradeoffs throughout the entire design. * Multi-CPU simulation enabled through Magma’s Native Parallel Technology TM delivers silicon-accurate results for very large complex systems (5M transistors and more) such as wireless systems on chip (SoCs) and full-chip memory designs. * Electrically Exact Models TM (E2M) dramatically improve simulation performance by orders of magnitude with virtually no loss in accuracy compared to fast SPICE....

With the Cadence® SoC Encounter™ RTL-to-GDSII System, engineers can account for the effects of interconnect across the entire chip—from the outset of the implementation cycle. It combines RTL synthesis, silicon virtual prototyping, automated floorplan synthesis, clock network synthesis, design for manufacturability and yield, low-power and mixed-signal design support, and nanometer routing. It also offers the latest capabilities to support advanced 65nm and 45nm designs. Features/Benefits * Supports multiple implementation styles with built-in power-planning, floorplanning, and signal integrity analysis * Supports multiple methodologies for flip-chip implementation, promoting concurrent chip/package design * Provides a statistical static timing analysis solution and standardized ECSM library models * Incorporates cutting-edge yield and low-power design capabilities * Handles 50M+ gate designs at 90nm and below Encounter...

Technology Computer-Aided Design (TCAD) refers to the use of computer simulations to develop and optimize semiconductor processing technologies and devices. Synopsys TCAD software solves fundamental, physical partial differential equations, such as diffusion and transport equations, to model the structural properties and electrical behavior of semiconductor devices. This deep physical approach gives TCAD simulation predictive accuracy for a broad range of technologies. Therefore, TCAD simulations are used to reduce the costly and time-consuming test wafer runs when developing and characterizing a new semiconductor device or technology. Synopsys TCAD tools are used by all leading semiconductor companies throughout the technology development cycle. At the early stage of technology development, TCAD tools allow engineers to explore product design alternatives such as engineering the...

ICX / TAU ICX® and ICX Pro provide an intuitive user interface for engineers to explore signal integrity solutions in their high-speed designs. Engineers learning signal integrity are offered a concise view of how things work, while those more seasoned are able to investigate signal integrity effects in their designs in great detail. Components are modeled using industry standard IBIS models, with support for virtually all IC model types, while simulations are provided by our proven ICX simulation technology. With a library of default IBIS models provided, engineers can begin evaluating high-speed design solutions easily and quickly. The Tau® board-level symbolic timing analysis tool performs comprehensive worst-case timing analysis and verification on designs using an advanced symbolic timing methodology, eliminating...