EDA Design Page 163

IntelliSuite 8.2 can Used by MEMS professionals worldwide for design, development and manufacturing of MEMS, IntelliSuite has firmly established itself as industry’s standard tool.  As such, IntelliSense provides MEMS companies and individual users with a complete living design environment. IntelliSuite is a tightly integrated design environment that will link your entire MEMS organization together. Built to scale from a point tool to an organization-wide tool, IntelliSuite unifies various engineering and manufacturing tasks into a single living design environment. Designed around collaboration, IntelliSuite allows the design and process teams collaborate on MEMS devices that can be prototyped and manufactured with fewer costly iterations. IntelliSuite starts the design process from fabrication machine settings, rather than device geometry — an approach that helps...

CoWare, Inc. has announced a major new release of its SystemC-based ConvergenSC SoC design tools to speed adoption of electronic system level (ESL) design methodologies by system designers and architects. The release combines new features that enable faster modeling and debug of IP models, platform subsystems, and SoC designs in SystemC, with an open environment that eases integration of internal tools and IP into the system-level flow. ConvergenSC now features a powerful SystemC integrated development and debug environment (IDE) based on Eclipse — the leading C++ development environment for embedded software — adding SystemC graphical debugging and a managed builds process to ConvergenSC\’s fast SystemC simulator and thread-aware debugging engine. Because Eclipse is open, users can easily integrate Eclipse plug-ins...

CoWare Processor Designer 2009.1 Programmable Accelerators for Platform-Driven ESL Design Integrated design environment for unified application specific processor, programmable accelerator design and software development tool generation Slashes application specific processor and programmable accelerator hardware design time by months Eliminates months of engineer-effort for software tool development Ensures compatibility of instruction set simulator (ISS), software development tools and RTL implementation Software development environment enables application software development prior to silicon availability CoWare® Processor Designer is an automated, application-specific embedded processor design and optimization environment that slashes months from processor hardware design time and engineer-month from the creation of application processor-specific software development tools. Processor Designer\’s high degree of automation enables design teams to focus on architecture exploration and application-specific processor development,...

CoWare Signal Processing Designer 2009.1 Implementing Algorithms for Platform-Driven ESL Design Highlights Industry\’s fastest, production proven signal processing simulator Fully supported on Windows and Linux 4000+ models with source code Unique standards reference libraries Fully integrated with MATLAB® and Catalytic MCS tools Fully integrated into CoWare platform-driven ESL design solution RTL cosimulation support for Cadence Incisive® and Mentor Modelsim® RTL code generation for Synopsys DesignCompiler® and Cadence Encounter® Analog-Mixed Signal (AMS) cosimulation with Cadence Incisive® One-click analysis Powerful polymodeling capability State-of-the-art GUI for maximum productivity Scalable XML database Automated model migration from SPW designs OverviewCoWare® Signal Processing Designer (SPD) accelerates the design of complex, digital signal processing (DSP) systems. It is a C-based modeling and simulation environment that facilitates structured...

Denali PureSuite 3.2.062 Linux64 is the industry\’s most complete compliance suite for exercising designs and measuring compliance with the PCI Expresss specification, and ensuring interoperability with other PCI Express designs. Used with the PureSpec&trade verification IP product, PureSuite provides a comprehensive, automated solution for functional verification of PCI Express designsProduct:Denali PureSuite 3.2.062 Linux64 Lanaguage:English Platform:/Linux64 Size:5MB

Denali PureSuite 3.2 is the industry\’s most complete compliance suite for exercising designs and measuring compliance with the PCI Expresss specification, and ensuring interoperability with other PCI Express designs. Used with the PureSpec&trade verification IP product, PureSuite provides a comprehensive, automated solution for functional verification of PCI Express designsProduct:Denali PureSuite 3.2.062 Linux32 Lanaguage:English Platform:/Linux Size:137MB

Cadence  Incisive  Formal Verifier(IFV) allows design teams to start RTL block verification months earlier than when using traditional simulation-based techniques. Its formal, assertion-based approach and exhaustive analysis capabilities ensure verification quality by pinpointing the source of bugs and detecting the corner-case errors that other methods often miss. Incisive Formal Verifier integrates easily into established design and assertion-based verification flows through its support of industry-standard languages. Features/Benefits Speeds time to block design closure with early error detection, analysis, and debug Reduces risk of re-spin by finding bugs that other verification approaches miss Eases chip-level verification by delivering higher block-level verification quality Leverages the same assertions as Incisive simulation, acceleration, and emulation technologies Supports all industry-standard assertion formats, including SystemVerilog Assertions (SVA),...

# Algorithms including LMS, normalized LMS, leaky LMS, fast block LMS, sign LMS, RLS, and QR-RLS# Filtered-X LMS and normalized filtered-X LMS algorithm for active noise/vibration control# Examples including adaptive noise/echo cancellation, adaptive system identification, and LPC# Simulation and LabVIEW FPGA code generation for fixed-point LMS adaptive filter# Support for Windows 2000/XP/Vista/7 and LabVIEW Real-Time The NI LabVIEW Adaptive Filter Toolkit provides tools for designing, analyzing, and simulating adaptive filters, including both floating- and fixed-point. You can use these tools to create adaptive filters with various algorithms, such as least-mean-square (LMS) and recursive-least-square (RLS), as well as their variants. You can apply the adaptive filters you create to different applications, such as adaptive noise cancellation, adaptive echo cancellation, and system...

Well-maintained and consistent libraries are the keys to efficient design work in Expedition PCB®. The \”Library Manager™ for DxDesigner® to Expedition® PCB Flow\” course will give you the skills necessary to create, protect, add to and change the different data types in your Central Library. The lecture modules discuss the Central Library philosophy as well as how to use the Library Manager tools and how to best interface library objects into your design process. Hands-on lab exercises reinforce the lecture topics as you create a small library of symbols, parts, and cells from scratch under the guidance of our industry expert instructors.You will learn how to * Start a new Central Library and copy elements between libraries * Create partitions...

Agilent RF Design Environment (RFDE) provides access to the ADS circuit simulators directly from the Cadence Analog Design Environment (ADE). Note: RFDE is being replaced by Agilent\’s GoldenGate RFIC Design Software. RFDE 2009 is the last supported release. Agilent\’s GoldenGate is the leading RFIC Simulator platform delivering high capacity and unique analysis for full chip verification and design for yield. Developed for the specific needs of RFIC/Wireless designers, GoldenGate is fully integrated into the Cadence Analog Design Environment (ADE). ADS circuit simulators will continue to be accessible from ADE through the ADS Dynamic Link capability.Product:Agilent RF Design Environment (RFDE) 2008 Update2 Linux Lanaguage:english Platform:Winxp/Win7 Size:572MB