EDA Design Page 162

Opera provides the complete toolchain for electromagnetic design, simulation and analysis of results, for use on 32- or 64-bit Windows and Linux platforms. It consists of a powerful pre-processing environment for creating design models (or importing them from CAD programs), plus a powerful finite element analysis (FEA) solver from our range. Three generic solvers are optionally available: static electromagnetic fields (the widely used \’Tosca\’ tool) – low-frequency time-varying electromagnetic fields – high frequency time-varying electromagnetic fields* – Opera can alternatively be purchased in a number of forms optimised for specific design problems: linear and rotating machinery design – superconducting magnet quenching – space charge effects from particle beams – permanent magnet magnetisation/demagnetisation – thermal and stress analysis (standalone or coupled)...

Sigrity, Inc. today announced SpeedPKG Suite, a suite of analysis tools customized for IC package applications and designed to enable fast, easy, accurate and complete electrical characterization. In addition, the company announced availability of the first of many SpeedPKG modules, XtractIM, which helps IC package design teams assess package electrical performance issues much faster than previously possible. Rather than using static and quasi-static solvers to extract package RLGC parameters, XtractIM extracts package models from S parameters computed by full-wave field solvers, fully taking into account various electromagnetic interactions. Unlike tools that have to use symmetric circuit structures to represent non-symmetric physical structures, XtractIM correctly represents the non-symmetric nature of the physical structures by generating non-symmetric Pi and T type Spice...

Mician uWave Wizard 6.6 is a design tool using the well-known fast and accurate Mode-Matching technique. This method is particularly suitable for simulation and optimization of passive microwave systems and components, including antennas. The mode matching method (MM) and their derivatives (i.e. the fast hybrid MM/boundary contour and the MM/2D-finite-element method) is the only method capable of simultaneously offering fastest processing speed and highest accuracy. Mician’s software developers\’ secret for speed is to avoid the use of time consuming 3D solvers wherever possible and to focus on applying the Mode-Matching Technique and its derivatives instead, even on structures that at first glance seem to be suited for 3D solvers only. Yet, a 3D FEM solver on element level is available within...

:::::English Description:::::: µWave Wizard 7.0 is a design tool using the well-known fast and accurate Mode-Matching technique. This method is particularly suitable for simulation and optimization of passive microwave systems and components, including antennas. The mode matching method (MM) and their derivatives (i.e. the fast hybrid MM/boundary contour and the MM/2D-finite-element method) is the only method capable of simultaneously offering fastest processing speed and highest accuracy. Mician’s software developers secret for speed is to avoid the use of time consuming 3D solvers wherever possible and to focus on applying the Mode-Matching Technique and its derivatives instead, even on structures that at first glance seem to be suited for 3D solvers only. Yet, a 3D FEM solver on element level is available...

Zeland Product Suite 14.62-高性能电磁仿真和优化工具 ZELAND PRODUCTS          Versions:    Update Date  ZPM                    14.5          5/26/09  IE3D                   14.62         10/27/09  IE3D-SI (AGIF)         14.62         10/27/09  FIDELITY                5.72         8/29/08  MDSPICE                 3.91         8/29/09  ZDS/ZDM/JobsManager    14.60         7/21/09  EM Socket Link to MWO  14.18         8/30/08 ZELAND Releases and Patches: * IE3D 14.61 (10/27/2009)  – MGRID 14.62: Implemenation of powerful geometry editing command such as cropping and    removing of polygons from a region defined as a polygon; Implemenation of saved vertices    to ease geometry entry and editing related to other geometry information; Implementation    of customized layout view for easy editing of multi-layered structures; Improvement on    coupled port de-embedding.  – IE3D-SI (AGIF) 14.62: Much improvement on geometry operations; Release of Physical    Component Compiler Library on the IE3D-SI on MFC (agif_mfc.exe).* IE3D 14.61...

Aldec, Inc., announced today the release of Riviera-PRO 2008.06, a behavioral, structural and mixed HDL language simulator for multi-million gate ASIC and FPGA designs. Riviera-PRO 2008.06 includes Verilog® simulation performance enhancements, increased SystemVerilog support, seamless SystemC/C/C++ and HDL co-debugging in common environment and new support for SVA and PSL assertions in the Waveform Viewer. Riviera-PRO supports System Level Verification with SystemC and SystemVerilog, Assertions based verification, Open Verification Methodology (OVM), Electronic System Level (ESL) and STARC® based Linting. Verilog Simulation Performance Speed-upVerilog simulation speed at the gate level has been increased up to 2.3X over the previous release. Memory allocation during simulation has been significantly reduced, to enable larger solutions on 32 and 64 bit platforms. All mixed language designs...

ALINT™ is an RTL design analysis tool that identifies design issues early in the development cycle. VHDL, Verilog® or mixed-language designs are checked for coding inconsistencies, design structure issues, synthesis, simulation, clock and reset issues prior to simulation and synthesis. Powerful, graphical utilities are provided for violation analysis and debugging. ALINT significantly reduces verification time for complex FPGA and ASIC designs, which results in uniform, reusable and reliable code, reducing the risk of costly ASIC re-spins. Comprehensive rule sets are available for VHDL, Verilog and mixed-language designs. User-definable rules and extensive rule management features enable corporate standardization. Top Features * Fast design analysis of complex ASIC/FPGA/SOC designs * IEEE VHDL, Verilog and mixed-language designs * STARC VHDL or Verilog rule...

Mentor Graphics Corporation (NASDAQ: MENT) today announced that the Calibre® nmLVS product now provides comprehensive support for the iLVS interoperable rule specification used by TSMC for new design kits. This allows customers to define and customize complex IC design rules, as needed, while maintaining compliance with TSMC specifications and allowing seamless adoption of EDA vendor performance optimizations. The iLVS specification, which was co-developed by Mentor, TSMC and several other EDA partners, separates the rule definition syntax from underlying rule implementations. This allows Mentor to optimize the underlying implementation, reducing the need for users to tune the general rule specifications themselves. Moreover, by using iLVS in conjunction with the Calibre nmLVS Advanced Device Properties (ADP) facility, the Calibre tool users can...

Mentor Graphics PADS 9.0.2 With Update1 release is a full flow release that delivers major functional enhancements to DxDesigner® and HyperLynx® Analog..Please see more details below. DR 594360 – PADSPCB_Install-PADS Suites – Installing PADS 9.0 over PADS 9.0.1 clears the library list for Logic and Layout Problem:  If PADS 9.0.1 is installed over older PADS versions they can coexist without errors. However, when older PADS versions are installed over PADS 9.0.1, the installation process for the older software will not proceed normally due to incompatibilities between the older software and the version of installer used in PADS 9.0.1 which is newer.  The .ini files for PADS Logic and PADS Layout for the older software will not be created.  PADS libraries...

Key components * Integrated development environment with project management tools and editor * Highly optimizing C and C++ compiler for AVR * Automatic checking of MISRA C rules for safety-critical applications * Configuration files for all AVR Classic, ATmega and FPSLIC families, including devices with the enhanced core * JTAGICE mkll and AVR® ONE! debugger support * Run-time libraries * Relocating AVR assembler * Linker and librarian tools * C-SPY® debugger with AVR simulator and support for RTOS-aware debugging on hardware * Example projects for AVR and code templates * User and reference guides in PDF format * Context-sensitive online help Supported devicesIAR Embedded Workbench for AVR supports devices in all AVR families: Automotive AVR: ATtiny24 Automotive, ATtiny25 Automotive, ATtiny261...