EDA Design Page 160

Mentor Graphics HDL Designer Series 2009.2 combines deep analysis capabilities, advanced creation editors, and complete project and flow management, to deliver a powerful HDL design environment that increases the productivity of individual engineers and teams (local or remote) and enables a repeatable and predictable design process. Key Benefits Manages complex ASIC or FPGA designs in VHDL, Verilog and SystemVerilog Accelerates RTL Reuse Extensive design checking rules and rulesets Interactive HDL visualization and creation tools Automatic documentation features and reporting Intelligent debug and analysis Concurrent design entry and checking Design and Reuse Quickly assess reused code quality and increase design understanding Efficiently create RTL designs using text, tables, and graphics Interactively manage design flow and all project data Rapidly produce documentation...

IntelliSense IntelliSuite 8.5 contains a wide range of closely integrated tools to seamlessly go from schematic capture and optimization to design verification and tapeout. A flexible design flow allows you to start your design at either schematic, layout or 3D level. IntelliSuite consists of a number of advanced tools that work together. For instance, Synple allows you to capture your MEMS at a schematic level, much like SPICE for electrical circuits. Your design can then be quickly iterated and optimized at different granularities. Sophisticated synthesis algorithms can automatically convert your schematic into mask layout, 3D or better yet a meshed structure for full multiphysics analysis. Blueprint, is a physical design tool that incorporates advanced layout, design rule check, cross section...

Synopsys introduced its Synphony HLS (High Level Synthesis) solution that integrates M-language and model-based synthesis to deliver up to 10X higher design and verification productivity than traditional RTL flows for communications and multimedia applications. Synphony HLS creates optimized RTL for ASIC and FPGA implementation, architecture exploration and rapid prototyping. In addition, Synphony HLS complements C/C++-based flows by generating C-models for system validation and early software development in virtual platforms. Synphony HLS integrates with Synopsys\’ Design Compiler®, Synplify® Premier, Confirma™, VCS®, System Studio and Innovator products to deliver the most comprehensive prototyping, implementation and verification flows from algorithm to silicon. The Synphony HLS solution delivers significantly higher productivity than traditional methods by providing benefits such as: An automated flow from M...

Magma talus 1.1.5 Linux new Release. Digital Implementation Talus Platform  An all-new IC implementation system that offers unequaled automation and virtually unlimited capacity. With Talus, Magma provides true electronic design automation, rather than providing mere electronic design assistance, as traditional tools in the industry have. Dramatically reduces the design development cycle and design costs, and speeds yield ramp-up for very large ICs targeted at 65-nanometer (nm) and smaller process geometries. Core products include Talus Design, Hydra and Talus Vortex. With Talus Power Pro and Quartz Rail, Magma provides advanced low-power analysis and design capabilities. Product:Magma talus 1.1.5 Linux Lanaguage:english Platform:Winxp/Win7 Size:449MB

Cadence Encounter Test Version 9.1.100. Encounter Test provides full-function design for test (DFT) and automatic test pattern generation (ATPG) tools for logic design. Potential test problems are identified via ordered messages that enable Encounter Tests graphical analysis capability. Once a design is complete, the tools provide push-button ATPG that quickly delivers high test coverage for circuits ranging up to the largest in the industry. Starting Encounter Test and Diagnostics Encounter Test ships with execution shell scripts that can be used to invoke the Graphical User Interface. Once Encounter Test is installed, no other setup is required to start the process. product:Cadence Encounter Test 9.10 Linux Lanaguage:english Platform:Winxp/Win7 Size:1.13G

Wireless InSite is site-specific radio propagation software for the analysis and design of wireless communication systems. It provides efficient and accurate predictions of propagation and communication channel characteristics in complex urban, indoor, rural and mixed path environments. Remcom has a long history as a leading expert and innovator in high-fidelity propagation. We continue to focus on speed and power with Wireless InSite’s ongoing development. With each new release the product performs faster and handles ever more challenging computations. Applications range from military defense to commercial communications:  Wireless communication links  Antenna coverage  Jammer effectiveness In addition to enhancements that directly affect speed, new options increase capability and flexibility. In response to the popularity of the Wireless InSite Real Time API, the...

SystemVue is a focused EDA environment for electronic system-level (ESL)design that allows system architects and algorithm developers to innovatethe physical layer (PHY) of next-generation wireless and aerospace/defensecommunications systems. It provides unique value to RF, DSP and FPGA/ASICimplementers who rely on signal processing to deliver the full value of theirhardware platforms.SystemVue replaces general-purpose analog, digital and math environments byoffering a dedicated platform for ESL design and signal processing realization.SystemVue “speaks RF,” cuts PHY development and verification time in half, andconnects to your mainstream EDA flow.Key benefits• Best-in-class RF fidelity among today’s baseband/PHY environments, whichallows baseband designers to virtualize the RF and eliminate excess margin• Superior integration with test accelerates real-world maturity and streamlinesyour model-based design flow, from architecture to verification• World-class...

Product Announcement: ARM SoC Designer – Final Release v7.1 is Now Available CAMBRIDGE, UK – Aug.18, 2008 – ARM today announces the availability of SoC Designer version 7.1. This release provides several new benefits and enhancements and is the last release made by ARM. As per the agreement with Carbon Design Systems, Carbon has assumed future development, support and sale of the SoC Designer tool. Product Benefits * Faster loading of the component library thanks to caching support * Faster components creation with new IP-XACT and Verilog based modes * Remote Debugging using new TCP/IP based communication protocol for the CADI Server and Client * Link to Algorithmic level with updated Mathworks\’ Simulink co-simulation support * Easier and more powerful...

ARM [(LSE: ARM); (Nasdaq: ARMH)] today announces the availability of SoC Designer version 7.1. This release provides several new benefits and enhancements and is the last release made by ARM. As per the agreement with Carbon Design Systems, Carbon has assumed future development, support and sale of the SoC Designer tool. Product BenefitsProduct:ARM SOC DESIGNER 7.1 Linux Lanaguage:english Platform:Winxp/Win7 Size:108MB

Synopsys Synplify FPGA 2009.12 Linux As system complexities keep advancing, the complexity of programmable logic is following suit. High-density field programmable gate arrays (FPGAs) now contain millions of gates and operate at speeds in excess of 100 MHz. At this level of complexity, schedules, budgets and FPGA design tools all begin to feel the burden. Enter Synplify Pro® advanced FPGA synthesis solution. The Synplify Pro tool starts with all the features that made Synplify® software the industry\’s most popular and robust synthesis product, and moves beyond by providing additional capabilities. By using the Synplify Pro solution, you can push the performance of challenging and complex designs while remaining comfortably on or ahead of scheduleproduct:Synopsys Synplify FPGA 2009.12 Linux Lanaguage:english Platform:Winxp/Win7 Size:1.12G