EDA Design Page 161

TimingDesigner is a flexible, interactive timing analysis and diagram tool. Its intuitive use of timing diagrams and patented spreadsheet technology allow users to model their unique timing challenges, analyze a range of conditions, obtain accurate results as well as monitor and manage timing margins throughout the design processCadence Allegro PCB Signal Integrity (SI) Interface TimingDesigner® 9.2 now provides a seamless integration with Cadence® Allegro® PCB SI to aide in more accurate timing analysis. Joint signal integrity and timing analysis is becoming increasingly important as design speeds grow, margins shrink, and project schedules shorten. This enhanced integration allows users to import simulated interconnect delays from Allegro PCB SI, enabling design teams to resolve timing issues early in the design process when...

Today, engineering teams in the electronics industry face unprecedented challenges in product development characterized by shorter design cycles, stringent cost constraints, new feature requirements, and smaller geometries. In order to help you accelerate through these challenges EMA has developed TimingDesigner® Design Kits: pre-assembled timing diagrams of common design components complete with all specified libraries for speed and voltage ratings. Design Kits give designers a time saving head-start for static timing analysis of their designs. They provide all documented timing protocols associated with commonly used design components such as SDRAM and DDR memory, as well as several common processors and FPGA libraries. Each Design Kit Component is parameterized where applicable so that configuration options affecting timing relationships are accurately represented, and...

With SpeedXP 8.0, Sigrity is introducing user-customizable workflows to enhance productivity for both new and experienced users.  Sigrity is providing seven default workflows for use with PowerSI and SPEED2000 covering topics such as a model extraction workflow, power ground noise simulation workflow and EMC/EMI simulation workflow.  Sigrity provided workflows can be tuned to adapt to individual / team preferences and users can also easily create their own workflows.  ENHANCEMENT SUMMARY Here is a quick feature summary.   Software releases are available for electronic download at Sigrity\’s Customer Sign-In area. Primary user contacts have account user name and password information.   Password retrieval is available at the SPDnet site. SpeedXP (8.0 Production Release) Overall SpeedXP capability:  Customizable workflows … for user defined...

Mentor Graphics IC implementation solution, Olympus-SoC™, delivers innovative technologies to solve the power, performance, capacity, time-to-market, and variability challenges encountered at the leading-edge process nodes The Olympus-SoC netlist-to-GDSII system performs variation- and power-aware rapid feasibility, including placement, advanced clock tree synthesis, and optimization. It also includes litho-driven routing that addresses optical proximity correction (OPC), resolution enhancement technology (RET), and critical area analysis (CAA) early in the design cycle, ensuring faster timing closure for complex process rules. Benefits of Olympus tools: Boost IC performance with advanced multi-corner, multi-mode (MCMM) optimization Reduce power consumption in clock trees with MCMM clock tree synthesis Improve yield with DFM-aware routing to address lithography issues in a timing context during implementation Speed time-to-market with fewer design...

Mentor Graphics FormalPro v2007.1_0-1 Linux is the Mentor Graphics solution for gate-level regression testing of ASICs and ICs of 100,000 gates or more. FormalPro uses static formal verification techniques to prove that a design is functionally identical to its golden reference. Features Dramatically Reduces ASIC/FPGA Verification Time Compares two designs – RTL to gate for synthesis and ECOs – Gate to gate for layout spins – RTL to RTL for language conversion Highest capacity tool – Verifies multi-million gate – ASIC\’s as one Fastest route to correct design – Exact location of errors – Tests fixes within the verification session Advanced FPGA Support – Xilinx, Altera, Actel – FVI and VIF automated setup files – Huge productivity boost product:Mentor Graphics...

Featuring industry leading accuracy, throughput and ease of use, SiliconSmart® provides standard cell and I/O characterization and modeling for all popular design flows and supports advanced timing and power modeling. It is a complete library characterization and publishing system that produces production-ready models with minimal setup effort. For maximum performance, SiliconSmart HP (High Performance) embeds Magma’s high-speed SPICE simulator, FineSim™ SPICE, providing a 2x improvement in throughput. Both are backed by dependable worldwide customer support and provide the most reliable and shortest path to high-quality, production-ready nanometer models.   Adaptive parallel job manager provides the fastest throughput and is fully scalable to take advantage of an unlimited number of CPUs, delivering unrivalled performance utilizing the highest level of parallelism (on...

Filter Solutions, Filter Light, and Filter Free are comprehensive PC windows based filter synthesis and analysis software packages for lumped, distributed, active, switched capacitor, and digital filters. Filter Free is the freeware version with minimal functionality. Filter Light is the low cost version with expanded capabilities over Filter Free, and Filter Solutions is the fully functional version. Filter Light is the low cost version of Filter Solutions.Filter Solutions supports tall of the features of Filter Light plus many advanced features. Filter Light and Filter Solutions support the following desirable features: General: Filter Light and Filter Solutions: * Gaussian, Bessel, Butterworth, Legendre, Chebyshev Type I, Chebyshev Type II, Hourglass, Elliptic, Raised Cosine, Matched and Delay filters. * Low Pass, High Pass,...

SMC and Synopsys Collaborate to Validate Galaxy Custom Designer Solution with TSMC 28nm iPDK MOUNTAIN VIEW, Calif., June 9 /PRNewswire-FirstCall/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that it has collaborated with TSMC to validate Synopsys\’ custom design solution with TSMC\’s 28-nanometer (nm) interoperable process design kit (iPDK) and Analog/Mixed-Signal (AMS) Reference Flow 1.0. TSMC\’s 28nm reference phase-locked loop (PLL) design was used to validate Synopsys\’ comprehensive custom solution while demonstrating productivity-enhancing capabilities of the TSMC AMS Reference Flow 1.0. The validated solution from Synopsys includes the Galaxy Custom Designer® implementation, HSPICE® circuit simulation, CustomSim™ FastSPICE simulation, StarRC™ parasitic extraction and IC Validator physical verification solutions. Through...

Galaxy Custom Designer™ LE is the modern-era choice for layout entry and editing, enabling users to meet the challenges of today\’s fast-moving nanometer designs with little or no learning curve. As with all Custom Designer tools, layout editing tasks are accomplished with fewer clicks, quicker menu access, and less pop-up menu clutter. Architected from the ground up with maximum productivity in mind, Custom Designer LE enables ultra-fast layout editing with advanced P-cell support and time-saving layout automation through capabilities like intelligent multipart paths that maintain DRC correctness. An integral component of the full Custom Designer system, LE provides transistor-level layout and editing capabilities in a unified platform for both cell-based and mixed-signal custom content which speeds complex chip design and...

Cadence Encounter RTL Compiler 9.1 Linux allows engineers to look across the entire design as they employ concurrent optimization techniques, such as making tradeoffs among timing, area, and power. To maximize performance, decrease die size, reduce power consumption, and boost productivity, designers need a global synthesis solution that enables concurrent optimization of timing, area, and power. Encounter RTL Compiler, a key component of the Cadence Logic Design Team Solution, delivers production-proven global synthesis for faster, smaller, and low-power chips in less time. With its unique set of patented global-focus algorithms, combined with new physically-aware optimization and analysis, Encounter RTL Compiler cuts design time while ensuring the highest quality of silicon. Features/Benefits A well-balanced logic structure isolates critical paths and reduces power,...