EDA Design Page 46
Synopsys Hspice 2021.09 for linux he Gold Standard for Accurate Circuit Simulation As the ‘golden accuracy’ cornerstone of the PrimeSim™ Continuum, HSPICE®, now PrimeSim HSPICE, is seamlessly integrated with and empowered by other simulation engines in the continuum. PrimeSim HSPICE is the industry’s ‘gold standard’ for accurate circuit simulation and offers foundries-certified MOS device models with state-of-the-art simulation and analysis algorithms. With extensive usage in chip/package/board/backplane signal integrity simulation, cell and memory characterization, and analog mixed signal IC design, PrimeSim HSPICE is the industry’s most popular, trusted and comprehensive circuit simulator. PrimeSim Pro delivers industry leading performance and capacity for DRAM, Flash memory and mixed-signal verification product:Synopsys Hspice 2021.09 Lanaguage:english Platform:Linux/Macosx Size:1DVD
Mentor.Graphics AMSV 2021.1 for linux The AMSV (Analog/Mixed-Signal Verification) 2021.1 release combines the Analog FastSPICE (AFSTM) Platform and AMS Eldo Platform product lines into a single release. You can choose what to install at the product level: AFS package; AMS Eldo,Questa ADMS, ADiT package; ICanalyst; Kronos; Symphony. Analog FastSPICE Platform The world’s fastest nanometer circuit verification platform for analog, RF, mixed-signal, and custom digital circuits. Symphony Mixed-Signal Platform The industry’s fastest and most configurable mixed-signal solution to accurately verify design functionality, connectivity, and performance across A/D interfaces at all levels of the design. Solido Variation Designer A comprehensive suite of tools for variation-aware design and verification, enabling full design coverage in orders-of-magnitude fewer simulations, with the accuracy of brute-force techniques....
Synopsys Euclide 2020.12 SP1 Synopsys Euclide enables engineers to find bugs earlier and optimize code for design and verification flows by identifying complex design and testbench compliance checks during SystemVerilog and Universal Verification Methodology (UVM) development. Euclide accelerates correct-by-construction code development through context specific autocompletion and content assistance that is tuned for Synopsys VCS® simulation, Verdi® debug, and ZeBu® emulation, helping engineers to improve code quality during the entire project development cycle. Synopsys Euclide features on-the-fly incremental compilation, elaboration, pseudo-synthesis and rule checking, all of which are integrated into the editor and provide feedback in seconds. Euclide helps to minimalize implementation bugs in RTL and testbench, improving project convergence rate and eliminating patchy code. product:Synopsys Euclide 2020.12 SP1 linux Lanaguage:english...
Synopsys Embedit vQ-2020.03 SP1 for linux Synopsys provides a broad portfolio of high-quality, silicon-proven foundation IP, including memory compilers and non-volatile memory (NVM), logic libraries, and general-purpose I/O (GPIO), enabling system-on-chip (SoC) designers to lower integration risk and speed time-to-market.product:Synopsys Embedit vQ-2020.03 SP1 Lanaguage:english Platform:Linux/Macosx Size:3DVD
PathWave Advanced Design System (ADS) 2022 RF and Microwave Circuit Design RF applications are trending towards ever higher millimeter-wave (mmWave) frequencies. Integration densities now require correct assembly, simulation, and verification of multi-technology RF modules. PathWave Advanced Design System (ADS) enables intelligent integration of modules that interconnect RFIC, MMIC, laminate, wafer-level packaging, antenna, and PCB into dense 3D structures, which can avoid costly hardware failures. With PathWave ADS, you can achieve consistent and timely design wins through RF design verification against wireless standards derived from Keysight RF instrumentation expertise. prototype COMplex RF systems, Create New Breakthroughs RF system design challenges include mmWave frequencies, multiple antennas, complex modulation, beam steering, and sophisticated algorithms. Traditional methods like rough estimates, formulas on spreadsheets, and...
Cadence GENUS v20.10 FOR LINUX Key Genus Synthesis Solution features and capabilities include: Massively parallel architecture – The tool performs timing-driven distributed synthesis of a design across multiple cores and machines. All key steps in the synthesis flow leverage both multiple machines and multiple CPU cores per machine. Physically aware context generation – The complete timing and physical context for any subset of a design can be extracted and used to drive RTL unit-level synthesis with full consideration of chip-level timing and placement, significantly reducing iterations between chip-level and unit-level synthesis runs. Unified global routing with Innovus™ Implementation System – Genus Synthesis Solution and Cadence Innovus Implementation System, a next-generation physical implementation solution, share an enhanced 4X faster timing-driven global...
Cadence XceliumMain v20.09.009 Key Benefits Compile/build performance Automated parallel and incremental build Regression throughput Throughput from some single-core performance (including gate-level, RTL, and SV testbench) Throughput and productivity improvement with save/restore Faster regressions with machine learning Reduced latency Multi-core performance for long-pole tests Native support for advanced use cases X-propagation, low-power (UPF/CPF), mixed-signal, and constrained random Support for multiple compute platforms Supported on x86 and Arm servers Supported on the cloud product:Cadence Xcelium v20.09.009 Lanaguage:english Platform:Linux/Macosx Size:2DVD
Synopsys VCS vQ-2020.03 SP2 for linux VCS product:Synopsys VCS vQ-2020.03 SP2 Lanaguage:english Platform:Linux/Macosx Size:1DVD
ANSYS Apache RedHawk 2021 R1.1 ANSYS RedHawk is an industry standard power noise and reliability sign-off solution for your SoC designs. With a track record of thousands of designs in silicon, RedHawk enables you to create high-performance SoCs that are still power efficient and reliable against thermal, electromigration (EM) and electrostatic discharge (ESD) issues for markets such as mobile, communications, high-performance computing, automotive and Internet of Things (IoT). Sign-off Redhawk has been the go-to sign-off solution for all foundries and processes since 2006, enabling you to create robust, low-power, high-performance SoCs in the most advanced FinFET technology. This includes accurate self-heat and thermal-aware EM analyses. Performance RedHawk’s advanced Distributed Machine Processing (DMP) enables significantly higher capacity and better performance for...
Synopsys Coretools vR-2020.12 SP4 The Synopsys family of coreTools is a comprehensive set of intellectual property (IP) packaging and integration tools for use in a knowledge-based design and verification flow. The tools enable designers to realize maximum productivity gains when using IP in their desing. By using an IP-based design and verification flow with IP packaged for assembly, the risk configuration, and subsystem integration errors is virtually eliminated, and designers have seen over a 60% reduction in SoC or platform design time and achieve the highest QoR in the implementation of the design. The coreTool family includes:coreBuilder™ – a robust packaging tool that allows designers to capture the knowledge and design intent of the IP and provide graphical or command...