EDA Design Page 172

Designers increasingly use advanced multi-clocking architectures to meet the high-performance and low-power requirements of their chips. The 0-In® CDC verification solution focuses on the interaction between these clock domains. In fact, it addresses a number of critical verification issues that simply cannot be dealt with by simulation-based verification techniques. An RTL or gate-level simulation of a design (that has multiple clock domains) does not accurately capture the timing related to the transfer of data between clock domains. As a consequence, simulation does not accurately predict silicon behavior, and critical bugs may escape the verification process. The 0-In CDC verification solution rectifies this problem. The 0-In CDC verification solution sets the industry benchmark by providing the three essential elements for a...

  Mentor Graphics Design for Test v8 2009.1 Linux 确保设计能于制造后正确工作 DFT工具为设计的可测性增加了设计电路（RTL或者gate level） DFT工具为投入生产的设计生成测试组来检测其缺陷 基于DFT结果进行失效分析 product:Mentor Graphics Design for Test v8 2009.1 Linux Lanaguage:English Platform:/Linux Size:278MB

Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today announced that Cypress Semiconductor Corp. has successfully taped out its West Bridge™ Antioch™ peripheral controller multimedia 3G/3.5G mobile phone integrated circuit (IC) using the Synopsys Galaxy™ design platform RTL-to- GDSII low-power solution, including the PrimeRail dynamic power network analysis solution. The multithreshold CMOS (MTCMOS) power gating feature in the Galaxy design platform enabled Cypress to complete its ultra-low-power design with world-class performance and optimized standby current. PrimeRail, a key component of the Galaxy design platform, enabled peak current analysis for the multiple power domains of the Power Gating-based design during physical implementation. \”For our mobile phone chip design, we needed a solution that could address peak current problems...

FineSim Pro defines a new paradigm in full-chip circuit-level simulation, enabling the simulation of the most challenging analog/mixed-signal SoCs with SPICE accuracy and unprecedented performance. Diagram * Combination of accuracy and performance in a single executable allows large, mixed-signal designs to be simulated with very accurate SPICE and fast-SPICE solving techniques. This provides complete control of speed- versus-accuracy tradeoffs throughout the entire design. * Multi-CPU simulation enabled through Magma’s Native Parallel Technology TM delivers silicon-accurate results for very large complex systems (5M transistors and more) such as wireless systems on chip (SoCs) and full-chip memory designs. * Electrically Exact Models TM (E2M) dramatically improve simulation performance by orders of magnitude with virtually no loss in accuracy compared to fast SPICE....

With the Cadence® SoC Encounter™ RTL-to-GDSII System, engineers can account for the effects of interconnect across the entire chip—from the outset of the implementation cycle. It combines RTL synthesis, silicon virtual prototyping, automated floorplan synthesis, clock network synthesis, design for manufacturability and yield, low-power and mixed-signal design support, and nanometer routing. It also offers the latest capabilities to support advanced 65nm and 45nm designs. Features/Benefits * Supports multiple implementation styles with built-in power-planning, floorplanning, and signal integrity analysis * Supports multiple methodologies for flip-chip implementation, promoting concurrent chip/package design * Provides a statistical static timing analysis solution and standardized ECSM library models * Incorporates cutting-edge yield and low-power design capabilities * Handles 50M+ gate designs at 90nm and below Encounter...

Technology Computer-Aided Design (TCAD) refers to the use of computer simulations to develop and optimize semiconductor processing technologies and devices. Synopsys TCAD software solves fundamental, physical partial differential equations, such as diffusion and transport equations, to model the structural properties and electrical behavior of semiconductor devices. This deep physical approach gives TCAD simulation predictive accuracy for a broad range of technologies. Therefore, TCAD simulations are used to reduce the costly and time-consuming test wafer runs when developing and characterizing a new semiconductor device or technology. Synopsys TCAD tools are used by all leading semiconductor companies throughout the technology development cycle. At the early stage of technology development, TCAD tools allow engineers to explore product design alternatives such as engineering the...

ICX / TAU ICX® and ICX Pro provide an intuitive user interface for engineers to explore signal integrity solutions in their high-speed designs. Engineers learning signal integrity are offered a concise view of how things work, while those more seasoned are able to investigate signal integrity effects in their designs in great detail. Components are modeled using industry standard IBIS models, with support for virtually all IC model types, while simulations are provided by our proven ICX simulation technology. With a library of default IBIS models provided, engineers can begin evaluating high-speed design solutions easily and quickly. The Tau® board-level symbolic timing analysis tool performs comprehensive worst-case timing analysis and verification on designs using an advanced symbolic timing methodology, eliminating...

Sisoft Quantum-Sl 2008.10 SP4 is the recognized leader for high-speed design among electrical and signal integrity engineers, with a proven track record for addressing tough high speed design problems.  Quantum-SI\’s comprehensive analysis capabilities accurately predict system-level noise and timing margins while significantly reducing the time and effort required to perform analysis with traditional methods.  Quantum-SI\’s interface-centric analysis approach allows engineers to quickly and easily analyze an entire design for the composite effects of signal integrity, crosstalk and timing and achieve first pass success. Quantum-SI\’s advanced data and simulation management allows designers to easily simulate and manage thousands of simulations. Product:Sisoft Quantum-Sl 2008.10 SP4 Lanaguage:English Platform:/win2000/winxp Size:186MB

Novas Verdi 2009.04—自动化侦错系统针对数字设计的侦错提供了先进的解决方案。 The Verdi 自动化侦错系统 Verdi自动化侦错系统针对数字设计的侦错提供了先进的解决方案，其中的技术包括： • 了解设计中复杂与不熟悉的行为 • 将困难与琐碎的侦错过程自动化 • 整合多元且复杂的设计环境 详细介绍:节省一半侦错时间 Verdi自动化侦错系统让使用者能专注在更有价值的设计上，凭借以下的独特技术，大体上可减少至少百分之五十以上的侦错时间： • 使用独家的行为分析(Behavior Analysis)技术自动追踪设计行为 • 以各种不同且功能强大的窗口提取并呈现相关逻辑电路 • 展现设计, 断言(assertion), 以及testbench运作下的交互关系  Product:Novas Verdi 2009.04 Lanaguage:English Platform:/Linux Size:351MB

During European Microwave Week in Amsterdam, Computer Simulation Technology (CST) announced the release of Version 2009 of the electromagnetic simulation software CST STUDIO SUITE, including its flagship product CST MICROWAVE STUDIO (MWS). Researchers and design engineers use CST STUDIO SUITE for the analysis and optimisation of EM based components. By choosing the most appropriate solver technology, making use of sophisticated import filters, and automated optimization and parametric studies, design throughput can be significantly augmented. Users of CST STUDIO SUITE version 2009 will benefit from numerous enhancements, including a total revision of the tetrahedral frequency domain solver\’s mesh adaptation scheme, transient EM/circuit co-simulation, MPI based parallelization for the fast solution to large problems on clusters, and the porting of the user...