EDA Design Page 170

3D EM Simulation XFdtd® is a 3D EM simulation software package that provides engineers with powerful and innovative tools for modeling and EM simulation. It was designed to be simple and easy to use, but with the power to handle the toughest simulations that engineers face today.XFdtd Release 7 XF7 is the market\’s most modern 3D electromagnetic simulation software for FDTD-based modeling and simulation. XF7 simplifies workflow with an overall focus on the iterative nature of the design process. Remcom continues to invest in features and enhancements that improve the power, speed, and usability that have always been the core strengths of our software. Unique capabilities of XF7 include: * XACT Accurate Cell Technology resolves the most intricate designs with...

！ Optimizing designs for leakage and dynamic power helps designers reduce energy consumption and packaging costs. But these advanced low-power design methods also complicate the verification task, introducing risk during synthesis and physical implementation. Full-chip, gate-level simulation is not a practical or scalable methodology for verifying today’s large, complex designs. Cadence® Encounter® Conformal® Low Power enables designers to verify and debug multimillion-gate designs optimized for low power, without simulating test vectors. It combines low-power structural and functional checks with world-class equivalence checking to provide superior performance, capacity, and ease of use. Features/Benefits Minimizes silicon re-spin risk by providing complete verification coverage Detects low-power implementation errors early in the design cycle Verifies multimillion-gate designs much faster than traditional gate-level simulation Closes...

TINA v8 and TINA Design Suite v8 are upgrades of the earlier programs, TINA for Windows, TINA Plus for Windows and TINA PRO 5.0 5.5, 6.0 and 7.0 already in wide use throughout the world. New features of TINA v8 and TINA Design Suite v8 TINA v8 • Vista style installation and folder scheme• Behavioral building blocks, nonlinear controlled sources• Powerful Spice-VHDL co-simulation including MCUs• Finite State Machine (FSM) editor with VHDL generation• Flowchart editor and debugger for controlling MCUs (in v8.0 for PIC MCUs only)• Any number of MCUs in one circuit• Extended MCU catalog including PIC18, CAN and more• Execution time measurement and statistics for Transient Analysis• Hyperlinks can be added to schematics and to the diagram window•...

Encounter Timing System Accelerate design closure and signoff with a single view of timingEncounter Timing System serves both front-end logic designers looking for high-quality, high-throughput timing analysis and ease of use, as well as back-end implementation engineers requiring electrical analysis and a common timing engine for silicon-accurate signoff. With Cadence® Encounter® Timing System, designers benefit from a consistent, integrated, multi-CPU enabled, static timing analysis (STA) environment for place-and-route optimization and signoff verification, leading to faster design closure and better flow convergence. Encounter Timing System helps designers analyze and debug multimillion-gate designs with significant gains in productivity. Global timing debug pinpoints the root cause of timing and constraint issues at the push of a button. Sophisticated delay calculation ensures accuracy and...

The Cadence® rF SiP Methodology Kit accelerates the application of eDAtechnologies to system-in-package (SiP) designs for radio Frequency(rF) and wireless applications. it provides methodologies that maximizedesign productivity and predictability for customers leveraging theadvantages of SiP technology. An integrated set of products built aroundproven methodologies enables complete front-to-back SiP design andimplementation. All this is demonstrated on a segment representativedesign, resulting in reduced time to new products, increased functionaldensities, and higher system performance.CADENCE SIP DESIGN TECHNOLOGYCADENCE RF SIP METHODOLOGY KITManufacturers of high-performance consumer electronics areThe Cadence rF SiP Methodology Kit leverages new SiPturning to SiP design because it can provide a number oftechnologies and verified advanced methodologies for rF SiPadvantages over just SoC. in addition to reduced cost, lowerdesign. it enables wireless...

WASP-NET （WAveguide Synthesis Program for waveguide NETworks）6.7是德国MIG公司的产品，MIG公司成立于1993年，自成立之日起，便与世界领导厂商建立起合作关系，在空间领域、无线通信和微波市场取得了巨大的成功，赢得了国际范围内的广泛认可。MIG公司由德国不来梅大学著名的Fritz Arndt教授创建。25年多来，Arndt和他的同事一直致力于波导类器件和天线的快速设计和仿真算法研究，在模式匹配和有限元、矩量法、差分方法的混合方面一直保持着世界领先的水平，Arndt教授一人已经发表了超过200篇的国际学术论文。WASP-NET在业内第一个采用了快速MM（模式匹配法）与FE（有限元）/ MoM （矩量法）/ FD （有限差分）4种方法的混合求解技术，即保证了求解精度和灵活性，又大大提高了效率。在WASP-NET中，一个典型的波导滤波器从设计、仿真到优化，在普通的PC机上仅仅需要不到10分钟的时间；一个带功分馈电网络的248槽波导缝隙行波阵列，在512MB内存的笔记本电脑上分析一个频点仅需60秒钟。 Product:MIG WASP-NET 6.7 Lanaguage:English Platform:/win2000/winxp Size:325MB

GraphiCode announces the release of StackupBuilder, a new product that allows modeling of PCB builds in a graphic environment. This provides valuable information about the physical build of the board allowing for reduced material costs. StackupBuilder uses the same data structure as all current GraphiCode products allowing compatibility between products. StackupBuilder is a combination of client-based application with a web service providing additional crucial material information via a user controlled database and license security. This allows StackupBuilder to run without a security dongle. When a stackup has been created within StackupBuilder it can be saved in the GWK and GraphiCode has allowed GC-Prevue to be able to view this stackup information along with the Gerber information in order to allow...

Synopsys VCS 2008.12 Linux is the industry’s most comprehensive RTL verification solution in a single product, providing advanced bug-finding technologies, a built-in debug and visualization environment and support for all popular design and verification languages including Verilog, VHDL, SystemVerilog and SystemC™. The VCS solution’s advanced bug-finding technologies include full-featured Native Testbench, complete assertions and comprehensive code and functional coverage to find more bugs faster and easier. Additionally, the VCS Verification Library provides verification IP for today’s most popular bus standards. By natively integrating these technologies within its unique, single-compiler architecture, the VCS solution delivers up to 5X faster verification performance compared with using multiple, stand-alone tools. The VCS solution’s powerful debug and visualization environment minimizes the turnaround time to find...

Infolytica MagNet 6.27 Electric Motors and Generators Magnetic Levitation Transformers Actuators Sensors and NDT applications Induction Heating Loudspeakers Magnetic Recording Heads MRI Transcranial Magnetic Stimulation (TMS) MagNet’s accurate solving modules can compute the static, frequency dependent or quasi-static time varying electromagnetic field due to either permanent magnet, current distributions sources or both. Here are just some of MagNet\’s many useful features: Easy to use intuitive interface Integrated 2D and 3D design environment Tranisent analysis with linear, rotational or arbitrary motion Automatic, adaptive and thin layer meshing in 2D and 3D Import Pro/E, Inventor, DXF and SAT files Circuit modeler for simulating loads and drives Link to other packages, such as PSIM and Simulink©, for drive or circuit co-simulations Powerful parameterization...

SPEED software is designed for modern motors. It also links the motor design to the controller design, and it can pilot a design from its inception to the finite-element solution of advanced problems. SPEED software is available for induction motors (polyphase/1-phase); brushless permanent-magnet motors (square wave/sine wave); d.c. brush motors; switched reluctance motors; and synchronous reluctance motors. It runs on the IBM PC platform, so it is easy to equip multiple users in one company, including laptop users. It is easy to learn and use, with full documentation that includes extensive information on motor theory and design. SPEED software is fast, to ensure high productivity. It is written for motor engineers, but is also used for designing controllers and power...