EDA Design Page 156

 With the National Instruments LabVIEW Touch Panel Module, you can quickly create and deploy human-machine interface (HMI) applications to communicate with NI embedded real-time platforms such as Compact FieldPoint, CompactRIO, and Compact Vision System. These HMIs provide a means to display data from and control autonomous real-time systems. The NI LabVIEW Touch Panel Module includes tools for user interface development, as well as functions for communication, data analysis, and data storage. The LabVIEW Touch Panel Module is optimized for developing HMIs to Windows CE touch panel devices such as the NI TPC-2006. Each National Instruments touch panel computer includes one LabVIEW Touch Panel Module deployment license; there is no additional deployment cost for large industrial systems. Add decision-making capabilities to...

provides fast visualization of RTL, so that an engineer can easily understand, and implement existing code elements, whether in VHDL, Verilog or System Verilog. It is no longer possible to carry out all ASIC and SoC designs from scratch: elements of previous designs have to be re-used and third party IP blocks are embedded very often. But understanding the RTL for third party IP or legacy code is not always easy, making it time consuming and difficult to modify and integrate into the new design.Product:Concept rtlvision 4.7.1 Linux Lanaguage:english Platform:Winxp/Win7 Size:52MB

GateVision PRO 4.7.1 linux is the third generation of graphical netlist analyzers from Concept Engineering. Completely rewritten to run on modern 32/64bit platforms, GateVision PRO provides the designer of even the largest chips with intuitive design navigation, schematic viewing, logic cone extraction and interactive logic cone viewing for debug support and design documentation. Using Verilog or EDIF netlists, GateVision PRO fits seamlessly into any design environment. The power of the underlying algorithms allows schematics to be created on the fly and the intuitive GUI lets the designer search for critical paths, for paths between specific components or for specific areas in the design. These can be bookmarked for future use, or cross-probed between different design views. Product:Concept gatevision 4.7.1 linux Lanaguage:english...

GateVision PRO is the thirdgeneration of graphical net-list analyzers from ConceptEngineering. Completely rewritten to runon 32/64bit platforms, GateVision PROprovides the designer of even the largestchips with intuitive design navigation,schematic viewing, logic cone extractionand interactive logic cone viewing fordebugsupportanddesigndocu-mentation.Using Verilog or EDIF netlists, GateVisionGraphical netlist analyzer − Verilog or EDIF netlistsPRO fits seamlessly into any designenvironment. The power of the under-Tcl based UserWare API – for advanced customizationlying algorithms allows schematics to be32/64 bit database handles today’s largest SoCs, ASICs and FPGAscreated on the fly and the intuitive GUIIntuitive GUI for ease of uselets the designer search for critical paths,Customizable path extraction engine finds critical pathsfor paths between specific componentsCone view extracts schematic fragments of critical areasor for specific areas in...

Concept SGvision PRO 4.7.2 linux is a new tool to analyze mixed level descriptions, both top level structures described in Verilog and lower level structures described via SPICE, can be debugged in a single integrated environment. To optimize or debug a device a designer may choose to work at transistor-level for critical areas such as IP/Library components and analog blocks, while staying at gate-level for other areas of the design. Debugging such a design has previously required separate tools: with SGvision PRO, it is now possible to see the schematics and traverse the signal flow of both the gates and the transistors in the same window, improving understanding of the circuits and accelerating analysis and debugging. Product:Concept sgvision 4.7.1 linux...

SGvision PRO 4.7.1 Win is an easy-to-use, very high performance and high capacity tool that is customizable via a tcl-based UserWare API (application programming interface), which allows designers to extend the functionality of SGvision PRO to meet the immediate needs of the project. Mixed mode graphical analyzer — Verilog and SPICE in a single tool. As detailed as you want — Debugging at gate-level and transistor-level. Logic cone — debug selected fragments or critical paths. 32/64 bit database — handles the largest SoCs and ASICs. Tcl based UserWare API — for advanced customization. Cookie cutting — SPICE fragments can be saved as separate SPICE files. Tcl based API — he Tcl Based UserWare API provides very flexible customization options, allowing SGvision...

Concept Engineering SPICEVISION 4.5.2 Linux Graphical netlist analyzer — pre-layout and post-layout SPICE Tcl based UserWare API — for advanced customization 32/64-bit database handles today′s largest SoCs and ASICs Exports schematics and schematic fragments — Cadence Virtuoso and EDIF 2.0.0 Cone display — Cone Window displays selected fragments and critical paths Cookie-cutting — fragments can be saved as separate SPICE files Customization — a Tcl based application program interface (API) allows access to the internal database and graphical user interface (GUI). Users can analyze the design data and generate user-specific design reports and design checks. Multi-level — the browser displays multiple hierarchy levels, from top level overview to all sub-circuit levels, while multiple windows display the hierarchy tree, source code...

SpiceVision PRO 4.7.1 takes the complex SPICE descriptions produced by many EDA tools and generates clean, easy-to-read transistorlevel schematics and circuit fragments, and design documentation to speed up debugging and project development. Spice circuits and models are the common currency of the EDA world. They are generated by many EDA tools and provide a description of the circuit at the lowest level of components: the transistors, capacitors, resistors and even the interconnect, that combine to produce, for example, an IC. But for all but the most trivial design, Spice files are difficult to read. SpiceVision generates circuit schematics on screen and speeds up debugging and project development. The SpiceVision product family helps to solve design problems in: Digital Circuits, Mixed-Signal...

RTLvision® PRO 4.7.1 provides fast visualization of RTL, so that an engineer can easily understand, and implement existing code elements, whether in VHDL, Verilog or System Verilog. It is no longer possible to carry out all ASIC and SoC designs from scratch: elements of previous designs have to be re-used and third party IP blocks are embedded very often. But understanding the RTL for third party IP or legacy code is not always easy, making it time consuming and difficult to modify and integrate into the new design. Product:Concept rtlvision 4.7.1 Win Lanaguage:English Platform:/WinNT/2000/XP Size:16.0MB

HSPICE 2010.03 Linux is the industry s gold standard for accurate circuit simulation and offers foundry-certified MOS device models with state-of-the-art simulation and analysis algorithms. With over 25 years of successful design tapeouts, HSPICE is the industry s most trusted and comprehensive circuit simulator. Design ChallengesAs IC geometries continue to shrink, the need for an accurate circuit simulator is critical. Designers require a highly accurate circuit simulator to precisely predict the timing, power consumption, functionality, and yield of their designs. As board and package speeds increase, designers need to employ increasingly accurate signal integrity analysis. SolutionHSPICE <!– Key Benefits –> Accuracy Gold standard for accurate circuit simulation. Extensive model support of the most accurate and expansive set of industry-standard and...