EDA Design Page 155
IAR Embedded Workbench® for ARM Integrated development environment and optimizing C/C++ compiler for ARMIAR Embedded Workbench with its optimizing C/C++ compiler is an integrated development environment for building and debugging ARM-based embedded applications. It provides extensive support for a wide range of ARM devices, hardware debug systems and RTOSs and generates very compact and efficient code. Ready-made device configuration files, flash loaders and over 1400 example projects are included. IAR Embedded Workbench is compatible with other ARM EABI compliant compilers and supports the following ARM cores: * ARM7 (ARM7TDMI, ARM7TDMI-S and ARM720T) * ARM7E (ARM7EJ-S) * ARM9 (ARM9TDMI, ARM920T, ARM922T and ARM940T) * ARM9E (ARM926EJ-S, ARM946E-S and ARM966E-S, ARM968E-S) * ARM10E (ARM1020E and ARM1022E) * ARM11 * SecurCore (SC000, SC100,...
IAR Embedded Workbench® for Renesas R32C Integrated development environment and optimizing C/C++ compiler for R32CIAR Embedded Workbench with its optimizing C and C++ compiler provides full support for devices in R32C series and generates very compact and efficient code. Built-in plugins to various hardware debug systems and RTOSs are included in standard edition. Key components * Integrated development environment with project management tools and editor * Highly optimizing C and C++ compiler for R32C * Configuration files for all devices in R32C family * Renesas E30 emulator debugger support * Run-time libraries * Relocating R32C assembler * Linker and librarian tools * C-SPY® debugger with R32C simulator and support for RTOS-aware debugging on hardware * Example projects and code...
IAR Embedded Workbench® for TI MSP430Integrated development environment and optimizing C/C++ compiler for MSP430IAR Embedded Workbench with its optimizing C/C++ compiler provides extensive support for devices in MSP430 and MSP430X families and generates very compact and efficient code. Built-in plugins to various hardware debug systems and RTOSs are included in the standard edition. Highlights in version 5.10Download free 30-day evaluation edition * C99 support * Support for new TI MSP430 devices * Improved optimizations For more details, see Product News. Key components * Integrated development environment with project management tools and editor * Highly optimizing C and C++ compiler for MSP430 * Configuration files for all MSP430 devices, including MSP430x5xx * FET debugger support * Run-time libraries * Relocating MSP430...
ETAP PowerStationAn Intelligent Simulator for Design, Analysis, Maintenance, and Operation of Electrical Power SystemsA fully integrated graphical simulator that works directly with one-line diagrams (ac and dc), coordination curves, cable raceways, ground grids, panels, and more. ETAP PowerStation Management System (PSMS™)Online Monitoring, Simulator, and Supervisory ControlBring your PowerStation model to life! As an extension to PowerStation, PSMS is a fully customizable application designed to provide engineering analysis, remote monitor, control, and simulation of induatrial and power utility systems, generation plants, and industrial facilities.Product:Etap PowerStation 6.0 Lanaguage:english Platform:Winxp/Win7 Size:489MB
Eplan Electric P8 1.9.11 多国语言含简体中文版 通过我们的EPLAN Electric P8，我们发起了工程中的新维数。多种功能广阔的范围使各学科间的全球协作成为现实。可以在图形和目标方位之间自由的选择，我们的软件为您的成功提供尖峰技术，它自身修改对用户的需求没有限制。这确保软件操作的可靠性和快速的效果。 独特的期待 EPLAN Electric P8知道您需要什么。它为完美的结合和有效的工作流程提供了变量技术，不同的界面，和广泛的自动操作。简而言之，EPLAN Electric P8为您的各学科之间的工程提供前所未有的机会。 电气工程的下一个维数 EPLAN Electric P8-电气工程中的新维数使绘图和目标导向同时工作。使用独特的平台技术，EPLAN 5 和 EPLAN 21支持的全部数据，变量技术，国际化，和广泛的自动操作，EPLAN Electric P8开创了生产力的开端。 由于独特的工程平台，这个创新的解决方案可以灵活的按照您的需求进行配置。大量不同的界面使有效的工作流程更简单的结合。简而言之，EPLAN Electric P8是各学科间的电气工程的无限的无约束的解决方案。 Product:Eplan Electric P8 1.9.11 Lanaguage:English Platform:win2000/winxp/win2003 Size:906MB
ispLEVER is the complete design environment for the latest Lattice programmable logic products. It includes a comprehensive set of powerful tools for all design tasks, including project management, IP integration, design planning, place and route, in-system logic analysis, and more. ispLEVER 8.0 SP1 ispLEVER® 8.0 Service Pack 1 (SP1) is now available. This software release includes an update to the support of the LatticeECP3 FPGA family including enhanced support of generic DDR interface, enhanced support of DDR3 memory interface, and improved targeting of the sysDSP™ block. An updated version of Synopsys® Synplify Pro® for Lattice (D2009.12L) and Aldec® Active-HDL™ Lattice Edition (8.2 update 3) are included in 8.0 SP1. Product:Lattice ispLever 8.0 SP1 Lanaguage:english Platform:Winxp/Win7 Size:1.83G
IntroductionThis Tutorial will help you to become familiar with operation Aldec Active-HDL simulator in the LatticeispLEVER environment. No prior knowledge of HDL simulation tools is required, but elementaryknowledge of VHDL and Verilog will be helpful.If you want to refresh your VHDL/Verilog, you are welcome to use our Interactive Tutorials: justgo to the Help menu in Active-HDL GUI, and then select the Interactive VHDL Tutorial orInteractive Verilog Tutorial option. The same tutorial is also accessible directly from theinstallation CD.After reading this tutorial, you will be able to launch Active-HDL simulator from ispLEVER, compile and runand debug functional simulation and post-route timing simulations.Configuring ispLEVER to launch Aldec Active-HDL simulator1. Double-click the ispLEVER icon on your desktop.2. Click on the Options tab in...
明導國際(Mentor Graphics)日前宣佈針對PCB系統設計推出新型Expedition Enterprise流程。包含用于Win的第二个升级包。 該流程能夠幫助大型電子公司全面product:Mentor Graphics Expedition Enterprise 2007.8 update2 Win Lanaguage:English Platform:/WINXP/WIN2003 Size:1.04G
::::::English Description:::::: Design Capture™ is a state-of-the-art front-end design package. Driving a full suite of digital and analog simulation and design tools, Design Capture enables you to rapidly and easily realize your design concepts, bringing them to life faster, and more accurately and profitably than ever before. Design Capture gives you the freedom to use traditional schematic-based entry with methods that are already familiar and comfortable to you. During creation, designs may be partitioned into various functional blocks and represented with different levels of hierarchy. Each level is readily described using either schematics or HDLs. Designs are also easily captured using your choice of top-down, bottom-up and middle-out methodologies, allowing complex systems to be easily represented and traversed.product:Mentor Graphics Design...
::::::English Description:::::: Want a powerful, yet easy to use simulation environment? SynaptiCAD’s simulation and debugging tools provide a standard interface for controlling all of your simulation tools. SynaptiCAD’s timing diagram editors have the most extensive and accurate timing analysis features available in any timing diagram editor on the market including delay correlation, reconvergent fan-out, and clocks that model jitter and buffer delays. Three different levels of editing let you pick the best price and feature set for your application. Free yourself from the time-consuming process of manually writing Verilog, VHDL, and SystemC test benches. Generate them graphically from timing diagrams. SynaptiCAD provides 3 levels of test bench generation to meet all your design needs. SynaptiCAD offers support for the...