EDA Design Page 153

Concept SGvision PRO 4.7.2 linux is a new tool to analyze mixed level descriptions, both top level structures described in Verilog and lower level structures described via SPICE, can be debugged in a single integrated environment. To optimize or debug a device a designer may choose to work at transistor-level for critical areas such as IP/Library components and analog blocks, while staying at gate-level for other areas of the design. Debugging such a design has previously required separate tools: with SGvision PRO, it is now possible to see the schematics and traverse the signal flow of both the gates and the transistors in the same window, improving understanding of the circuits and accelerating analysis and debugging. Product:Concept sgvision 4.7.1 linux...

SGvision PRO 4.7.1 Win is an easy-to-use, very high performance and high capacity tool that is customizable via a tcl-based UserWare API (application programming interface), which allows designers to extend the functionality of SGvision PRO to meet the immediate needs of the project. Mixed mode graphical analyzer — Verilog and SPICE in a single tool. As detailed as you want — Debugging at gate-level and transistor-level. Logic cone — debug selected fragments or critical paths. 32/64 bit database — handles the largest SoCs and ASICs. Tcl based UserWare API — for advanced customization. Cookie cutting — SPICE fragments can be saved as separate SPICE files. Tcl based API — he Tcl Based UserWare API provides very flexible customization options, allowing SGvision...

Concept Engineering SPICEVISION 4.5.2 Linux Graphical netlist analyzer — pre-layout and post-layout SPICE Tcl based UserWare API — for advanced customization 32/64-bit database handles today′s largest SoCs and ASICs Exports schematics and schematic fragments — Cadence Virtuoso and EDIF 2.0.0 Cone display — Cone Window displays selected fragments and critical paths Cookie-cutting — fragments can be saved as separate SPICE files Customization — a Tcl based application program interface (API) allows access to the internal database and graphical user interface (GUI). Users can analyze the design data and generate user-specific design reports and design checks. Multi-level — the browser displays multiple hierarchy levels, from top level overview to all sub-circuit levels, while multiple windows display the hierarchy tree, source code...

SpiceVision PRO 4.7.1 takes the complex SPICE descriptions produced by many EDA tools and generates clean, easy-to-read transistorlevel schematics and circuit fragments, and design documentation to speed up debugging and project development. Spice circuits and models are the common currency of the EDA world. They are generated by many EDA tools and provide a description of the circuit at the lowest level of components: the transistors, capacitors, resistors and even the interconnect, that combine to produce, for example, an IC. But for all but the most trivial design, Spice files are difficult to read. SpiceVision generates circuit schematics on screen and speeds up debugging and project development. The SpiceVision product family helps to solve design problems in: Digital Circuits, Mixed-Signal...

RTLvision® PRO 4.7.1 provides fast visualization of RTL, so that an engineer can easily understand, and implement existing code elements, whether in VHDL, Verilog or System Verilog. It is no longer possible to carry out all ASIC and SoC designs from scratch: elements of previous designs have to be re-used and third party IP blocks are embedded very often. But understanding the RTL for third party IP or legacy code is not always easy, making it time consuming and difficult to modify and integrate into the new design. Product:Concept rtlvision 4.7.1 Win Lanaguage:English Platform:/WinNT/2000/XP Size:16.0MB

HSPICE 2010.03 Linux is the industry s gold standard for accurate circuit simulation and offers foundry-certified MOS device models with state-of-the-art simulation and analysis algorithms. With over 25 years of successful design tapeouts, HSPICE is the industry s most trusted and comprehensive circuit simulator. Design ChallengesAs IC geometries continue to shrink, the need for an accurate circuit simulator is critical. Designers require a highly accurate circuit simulator to precisely predict the timing, power consumption, functionality, and yield of their designs. As board and package speeds increase, designers need to employ increasingly accurate signal integrity analysis. SolutionHSPICE <!– Key Benefits –> Accuracy Gold standard for accurate circuit simulation. Extensive model support of the most accurate and expansive set of industry-standard and...

Synopsys IC Compiler 2009.06 SP5 Linux new release. IC Compiler – A Comprehensive Solution IC Compiler uses Extended Physical Synthesis (XPS), a significant capability that extends physical synthesis to full place-and-route. XPS enables faster turnaround time (TAT) as well as better QoR, measured in terms of the complete cost vector — timing, area, power, signal integrity, routability, and yield. IC Compiler is tightly correlated to the industry-standard signoff solutions—PrimeTime® SI and StarRC™. Additionally, it utilizes these signoff engines to achieve fast, accurate signoff driven design closure during the final changes of physical design implementation. Signoff driven design closure further increases design predictability. IC Compiler provides a comprehensive DFM solution that concurrently optimizes for yield with timing, area, power, test, and...

Formality® is an equivalence-checking (EC) solution that uses formal, static techniques to determine if two versions of a design are functionally equivalent. The size and complexity of today’s designs, coupled with the challenges of meeting timing, area, power and schedule, requires that the newest, most advanced synthesis optimizations be fully verifiable. Formality supports all of the out-ofthe- box DC Ultra optimizations and so provides the highest quality of results that are fully verifiable. Formality supports verification of power-up and power-down states, multi-voltage, multi-supply and clock gated designs. Formality’s easy-to-use, flow-based graphical user interface and auto-setup mode helps even new users successfully complete verification in the shortest possible time. PDFDownload Datasheet Key benefits * Perfect companion to DC Ultra – supports...

The Synplify Premier solution is the industry\’s most productive FPGA implementation and debug environment. It includes all the features of Synplify Pro and additionally provides a comprehensive suite of tools and technologies for advanced FPGA designers as well as ASIC prototypers targeting single FPGA-based prototypes. The Synplify Premier software delivers fast turnaround time capabilities and feedback for users seeking to quickly implement the design on the board or to tune their design projects prior to final implementation. It addresses the most challenging aspects of FPGA design including timing closure and has the ability to perform graph-based physical synthesis for more accurate upfront timing prediction. It provides flows for fast logic verification and RT-Level debug. Under the hood, it contains optimization...

Synopsys introduced Design Compiler® 2010, the latest RTL synthesis innovation within the Galaxy™ Implementation platform, which delivers a twofold speedup in the synthesis and physical implementation flow. To meet aggressive schedules for increasingly complex designs, engineers need an RTL synthesis solution that enables them to minimize iterations to speed up physical implementation. To address these challenges, topographical technology in Design Compiler 2010 is being extended to produce \”physical guidance\” to Synopsys\’ flagship place-and-route solution, IC Compiler, tightening timing and area correlation to 5 percent while speeding up IC Compiler\’s placement phase by 1.5 times (1.5X). A new capability allows RTL designers to perform floorplan exploration within the synthesis environment to efficiently achieve an optimal floorplan. Additionally, Design Compiler\’s new scalable...