EDA Design Page 127

Optimizing designs for leakage and dynamic power helps designers reduce energy consumption and packaging costs. But these advanced low-power design methods also complicate the verification task, introducing risk during synthesis and physical implementation. Full-chip, gate-level simulation is not a practical or scalable methodology for verifying today’s large, complex designs. Encounter® Conformal® Low Power enables designers to create power intent, then verify and debug multimillion-gate designs optimized for low power, without simulating test vectors. It combines low-power structural and functional checks with world-class equivalence checking to provide superior performance, capacity, and ease of use. Features/BenefitsReduces the risk of silicon re-spins by providing complete verification coverageDetects low-power implementation errors early in the design cycleVerifies multimillion-gate designs much faster than traditional gate-level simulationCloses...

Cadence Design Systems acquired Altos Design Automation. Terms of the acquisition were not disclosed. Altos is a leader in foundation IP enablement. The company has over 30 customers, including 11 of the top 20 semiconductor companies. Altos Design Automation specializes in enabling foundation IP development for the delivery of complex SoCs at advanced nodes. Foundation IP characterization is becoming mission critical at advanced nodes due to shrinking time-to-market windows, escalating low-power, high-speed design complexities, and variations in advanced processes. Altos’ solutions enable fast and accurate characterization of memory, standard cell libraries and other foundation IP. Their tools generate required models for SoC implementation. When combined with the Cadence end-to-end Silicon Realization portfolio, Altos tools improve visibility into the effects of...

AWR Corporation, the innovation leader in high-frequency EDA software, has announced AWR Design Environment™ V10.04, its first new software release in 2013, which includes many new features and enhancements to Microwave Office®/Analog Office® circuit design software and Visual System Simulator™ (VSS) system design software, as well as AXIEM® 3D planar electromagnetic (EM) software and Analyst™ 3D finite element method (FEM) EM software. A select subset of new features and enhancements in AWR V10.04 include: Microwave Office/Analog Office Environment New MMIC Getting Started Guide New SDELTAM measurement Enhancements to optimization algorithms and yield analyses Expanded output file support across circuit simulators New scripts to reset the origins for layoutAnalyst 3D FEM EM Technology Up to 80 percent reduction in simulation time...

ey benefits of XF7 software include: XStream GPU Acceleration for CPUs and GPU clusters enables calculations to finish in minutes as compared to hours. Use XStream with the GPUs in a single computer or link multiple GPU clusters in parallel via MPI + GPU technology for massive EM calculations.Unlimited Memory support for problems exceeding 60 GB and billions of cells.External Queue Integration (EQI) allows XFdtd users in HPC environments to submit/queue their simulations directly to the compute cluster through the user interface.XACT Accurate Cell Technology resolves the most intricate designs with fewer computational resources.CAD Merge seamlessly integrates new versions of CAD files into existing projects.XTend Script Library automates modeling and design with pre-loaded, customizable scripts for creating custom features.First EM...

OverviewIC Compiler is an integral part of the Synopsys Galaxy™ Implementation Platform that delivers a comprehensive design solution, including synthesis, physical implementation, low-power design, and design for manufacturability. IC Compiler is a single, convergent, chip-level physical implementation tool that includes flat and hierarchical design planning, placement and optimization, clock tree synthesis, routing, manufacturability, and low-power capabilities that enable designers to implement today’s high-performance, complex designs on schedule. Download Datasheet IC Compiler is a comprehensive place-and-route system; it provides best QoR in timing, area, power, signal integrity, routability, out-of the-box results and faster design closure. Multicore support throughout the flow delivers improved productivity. New technologies enable designers to handle gigascale, complex designs and meet tight project schedules. IC Compiler is tightly...

Key components: Integrated development environment with project management tools and editor Highly optimizing C and C++ compiler for ARM Automatic checking of MISRA C rules (MISRA C:2004) ARM EABI and CMSIS compliance Extensive HW target system support Optional I-jet and JTAGjet-Trace in-curcuit debugging probes Power debugging to visualize power consumption in correlation with source code Run-time libraries including source code Relocating ARM assembler Linker and librarian tools C-SPY® debugger with ARM simulator, JTAG support and support for RTOS-aware debugging on hardware RTOS plugins available from IAR Systems and RTOS vendors Over 3100 sample projects for evaluation boards from many different manufacturers User and reference guides in PDF format Context-sensitive online help Chip-specific support: Over 3100 example projects for evaluation boards...

MagNet v72D/3D ELECTROMAGNETIC FIELD SIMULATION SOFTWAREPREDICTING PERFORMANCE FOR BETTER DESIGNS MagNet v7 2D/3D simulation software for electromagnetic fields let\’s you rapidly model and predict the performance of any electromagnetic or electromechanical device: Electric Motors/Generators Magnetic Levitation Transformers Actuators Sensors/NDT Induction Heating Loudspeakers Magnetic Recording Heads MRI Transcranial Magnetic Simulations MagNet uses the finite element technique for an accurate and quick solution of Maxwell\’s equations. Each module is tailored to simulate different types of electromagnetic fields and is available separately for both 2D & 3D designs. Transient or Time-varying electromagnetic fields Non-linear analysis Second-order time stepping Resume Feature: pause at a particular time step for inspection Core losses, proximity effects and eddy currents Motion Supports rotational, linear and general (multiple degrees...

OptimizePI enables design teams to balance decoupling capacitor (decap) cost and performance for printed circuit boards (PCBs) and IC packages. Decap costs savings of 15% to 50% are typical. High performance is analytically assured for the power delivery system (PDS) at both a system and component level. OptimizePI is built on proven Sigrity hybrid electromagnetic circuit analysis technology in combination with our unique optimization engine to quickly pinpoint the best possible decap selections and placement locations. OptimizePI Data Sheet in PDF format OptimizePI Applications: Automatically selecting and placing decoupling capacitors Eliminating decap over-design for printed circuit boards and IC packages Reducing PDS cost for new designs and post-production products Developing effective decap guidelines for packaged components Recapturing design area by...

JMAG-Designer is a simulation software for electromechanical design striving to be easy to use while providing versatility to support users from conceptual design to comprehensive analyses.Eddy Current Loss Density Distribution of the GearFig. 1 shows the eddy current loss density distribution of the surface of the gear and the cross-section of a tooth top. Each cross-section shown in the figure is the XY-plane at the midway position of the tooth width. The magnetic field generated by the coil produces eddy currents on the gear tooth surface. This eddy currents are distributed on the surface of the gear due to the skin effect.In addition, it is apparent that eddy current loss distribution produced on the surface of the gear varies with...

EPLAN Pro Panel Professional: Virtual enclosure layout in 3D EPLAN Pro Panel Professional convinces through its deep degree of integration in the EPLAN platform and utilizes its manifold basic techniques such as the EPLAN device concept, the macro and options technology, access to the EPLAN Data Portal, etc. The design approach is individual: Optionally on the basis of a schematic or directly as layout of the enclosure in 3D. The devices provided for the mounting layout are displayed well-structured in Navigators or lists. During placing the system checks whether the positioning is carried out on the correct mounting panel. The innovative eTouch technology allows components to be comfortably aligned and positioned exactly. Installation regulations and minimum spacing to manufacturer specification...