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EDA Design Page 130

Cadence MMSIM v12.10.317

MMSIM 12.1 contains many new features to aid RF designers. Many of these changes are described in my Part 1 blog post. I\’ve saved my favorite for last….here\’s a preview of the changes to the nport component in MMSIM12.1. 1. The Edit Object Properties/Add Instance form has been revised for better usability. 2. For most S-parameter files, only the S-Parameter file name and the number of ports need to be specified. (See the red boxes in the GUI below). The default settings for all of the other properties are suggested. nport1a gui 3. When you select the Browse and select s-data file button, the following GUI appears and allows you to browse and select the desired s-parameter data file. Once...

Synopsys VCS Verification IP 2012.12

Industry-leading designers of today’s most advanced designs rely on the Synopsys VCS© functional verification solution for their verification environments. In fact, 90% of designs at 32nm and below are verified with VCS. Used by a majority of the world’s top 20 semiconductor companies as their primary verification solution,VCS provides the high performance simulation engines, constraint solver engines, Native Testbench (NTB) support, broad SystemVerilog support, verification planning, coverage analysis and closure, and an integrated debug environment. VCS has continually pioneered numerous industry-first innovations, and is now poised to meet the challenges and complexity of today’s SoCs. With features such as constrained random testbench, SoC optimized compile flow, coverage, and assertions, VCS has the flexibility and capabilities that are critical for today’s...

Cadence EDI 12.0

Cadence Encounter Digital Implementation v12Cadence® Encounter® Digital Implementation (EDI) System provides the most effective methodology to maximize performance, and minimize area and power for high-performance, giga-scale designs. Integration with the Virtuoso® custom design environment ensures seamless data transfer and increases productivity for mixed-signal designs. EDI System also supports advanced 20nm process technologies and system-in-package/3D-IC design. With these capabilities, EDI System delivers the most comprehensive solution for physical implementation of today’s most demanding designs. BenefitsPredictability and convergence Combines full-chip implementation with in-design signoff analysis in a single environment Enables design exploration and accurate chip feasibility analysis, including automated floorplan synthesis and ranking, as well as hierarchical budgeting and planning for convergent hierarchical implementation results New GigaOpt and CCOpt engines deliver better...

Frontline Genesis 2000 v9.9b3

Automating workflows from customer design to the production floor Genesis 2000 creates a seamless pre-production environment for automating processes, from the customer’s door to the production floor. Genesis 2000 combines planning, product engineering, and tooling into a single seat, supported by a unified ODB++ database. Add modular integration and an intuitive interface and you have unmatched bottom line results: higher throughput and measurable cost savings.Automation for speed and accuracy With the most extensive line-mode command access in the industry and embedded automation tools, you can automate planning, job analysis, editing, photo-tool creation, drill, rout, fixturing, AOI, electrical testing outputs, and workflow management. The accuracy of ODB++ contour-based algorithms means high repeatability, improved quality, and complete tooling consistency. ODB++ for data...

Xilinx.ISE.Design.Suite.v14.4

Xilinx introduced the ISE Design Suite software to enable breakthrough optimizations for power and cost with greater design productivity. For the first time, ISE design tools deliver \’intelligent\’ clock-gating technology that reduces dynamic power consumption by as much as 30 percent. The new suite also provides advances in timing-driven design reservation, AMBA 4 AXI4-complaint IP support for plug-and-play design, and an intuitive design flow with fourth-generation partial reconfiguration capabilities that lowers system cost for a broad range of high performance applications. With full production support for all Xilinx Virtex-6 and Spartan-6 FPGA families, the ISE release continues its evolution as the industry\’s only domain-specific design suite with interoperable design flows and tool configurations for logic, digital signal processing (DSP), embedded...

Silvaco TCAD 2012.3 for win

VICTORY Process3D PROCESS SIMULATOR VICTORY Process is a general purpose 3D process simulator. VICTORY Process includes a complete process flow core simulator and three advanced simulation modules: Monte Carlo Implant, Advanced Diffusion and Oxidation, and Physical Etch and Deposit. Proprietary models, as well as public domain research models, can be easily integrated into VICTORY Process using the open modeling interface.Key Features Sophisticated multi-particle flux models for physical deposition and etching with substrate material redeposition Extremely accurate and fast Monte Carlo implant simulation Comprehensive set of 3D diffusion models: Fermi, three-stream, and five-stream 3D physical oxidation simulation with stress analysis Fast 3D structure prototyping capability enables the in-depth physical analysis of specific processing issues Accurately predicts 3D topology and 3D dopant...

Synopsys Formality v2012.06

OverviewFormality® is an equivalence-checking (EC) solution that uses formal, static techniques to determine if two versions of a design are functionally equivalent. The size and complexity of today’s designs, coupled with the challenges of meeting timing, area, power and schedule, requires that the newest, most advanced synthesis optimizations be fully verifiable. Formality supports all of the out-ofthe- box DC Ultra optimizations and so provides the highest quality of results that are fully verifiable. Formality supports verification of power-up and power-down states, multi-voltage, multi-supply and clock gated designs. Formality’s easy-to-use, flow-based graphical user interface and auto-setup mode helps even new users successfully complete verification in the shortest possible time. PDFDownload Datasheet Key benefits Perfect companion to DC Ultra – supports all...

SynopSys PrimeTime v2012.12

PrimeTime® static timing analysis (STA) suite includes two key improvements that deliver a dramatic boost to designer productivity. This latest release includes a flexible multicore processing technology that makes more effective use of both single-core and multicore CPUs across today’s compute server farms, better harnessing their compute potential. This release also introduces new runtime optimizations, allowing design engineers to run faster full timing and signal integrity (SI) analysis on their large designs early in the implementation process, thus reducing costly design closure iterations. These improvements work in concert to deliver up to 2X faster runtime and have been confirmed on a suite of leading semiconductor companies’ designs ranging in size from one million to 50 million instances.product:SynopSys PrimeTime v2012.12 Lanaguage:english...

Synopsys Hspice vG-2012.06 SP1

The Gold Standard for Accurate Circuit Simulation HSPICE is the industry\’s \”gold standard\” for accurate circuit simulation and offers foundry-certified MOS device models with state-of-the-art simulation and analysis algorithms. With over 25 years of successful design tapeouts, HSPICE is the industry\’s most trusted and comprehensive circuit simulator. PDFHSPICE Datasheet For on chip simulation: Analog designs, RF design, custom digital design, standard cell design and characterization, memory design and characterization, and device model development. For off chip signal integrity simulation: Silicon to package to board to backplane analysis and simulation Design ChallengesAs IC geometries continue to shrink, the need for an accurate circuit simulator is critical. Designers require a highly accurate circuit simulator to precisely predict the timing, power consumption, functionality,...

Mentor Graphics Precision RTL 2012b

Precision Synthesis offers high quality of results, industry-unique features, and integration across Mentor Graphics’ FPGA Flow– the industry’s most comprehensive FPGA vendor independent solution.FPGA Synthesis Product Suite Precision RTL Plus Offers breakthrough advantages for both commercial applications and for mil-aero and safety-critical systems. Features include multi-vendor physical synthesis, incremental flows, low power synthesis, and IEEE-based encryption, and more. Precision RTL Plus + LeonardoSpectrum A single product to access both Precision RTL Plus and LeonardoSpectrum, Precision RTL Plus + Leo Station is an ideal upgrade for existing LeonardoSpectrum users. Precision RTL Offers an intuitive environment with advanced synthesis optimizations to deliver superior quality of results, award-winning analysis to eliminate defects, and advanced operator inference to enable FPGA vendor-independent design. Precision Physical...