EDA Design Page 113

TetraMAX ATPG Automatic Test Pattern Generation OverviewTetraMAX® ATPG automatically generates high quality manufacturing test patterns. It’s the only ATPG solution optimized for a wide range of test methodologies and integrated with Synopsys’ patented DFTMAX™ and DFTMAX Ultra, the leading test synthesis tools. The unparalleled ease-of- use and high performance provided by TetraMAX ATPG allows RTL designers to quickly create efficient, compressed test patterns for even the most complex designs. Key Benefits Improves product quality with comprehensive fault model support and power-aware test patterns Increases designer productivity by leveraging integration with Synopsys test compression tools Generates test patterns for even the largest and most complex SoCs Enables faster yield ramp by quickly isolating defect locations Features Extremely high capacity and performance...

VCS Functional Verification Choice of Leading SoC Design Teams OverviewIndustry-leading designers of today’s most advanced designs rely on the Synopsys VCS® functional verification solution for their verification environments. In fact, a high majority of designs at 32nm and below are verified with VCS. Used by a majority of the world’s top 20 semiconductor companies as their primary verification solution, VCS provides high-performance simulation engines, constraint solver engines, Native Testbench (NTB) support, broad SystemVerilog support, verification planning, coverage analysis and closure, an integrated debug environment, and offers X-propagation support (VCS Xprop) for X-related simulation and debug. VCS has continually pioneered numerous industry-first innovations, and is now poised to meet the challenges and complexity of today’s SoCs. With features such as such...

Leda 2014RTL Checker OverviewSynopsys\’ Leda® is a programmable design and coding guideline checker that delivers full chip mixed-language (Verilog and VHDL) and mixed representation (RTL & gate) capabilities to speed development of complex system-on-chip (SoC) designs. Leda’s pre-packaged rules greatly enhance a designer\’s ability to check HDL code for synthesizability, simulatability, testability, reusability, and RTL/gate signoff. Leda detects clock synchronization-related bugs, isolates hard-to-time circuits, verifies layout considerations and improves DFT for higher ATPG coverage. Leda comes prepackaged with rules to improve performance of Synopsys tools, such as VCS MX, DC and Formality. Key Benefits Finds design and coding guideline bottlenecks that impact simulation, synthesis, timing, DFT, ERC, and layout Enables design reuse with prepackaged guidelines, such as the Reuse Methodology...

Synopsys coreToolsIP Based Design and VerificationOverviewThe Synopsys family of coreTools is a comprehensive set of intellectual property (IP) packaging and integration tools foruse in a knowledge-based design and verification flow. The tools enable designers to realize maximum productivity gainswhen using IP in their desing. By using an IP-based design and verification flow with IP packaged for assembly, the riskconfiguration, and subsystem integration errors is virtually eliminated, and designers have seen over a 60% reduction inSoC or platform design time and achieve the highest QoR in the implementation of the design.The coreTool family includes:coreBuilder™ – a robust packaging tool that allows designers to capture the knowledge and design intent of the IPand provide graphical or command based configuration menus for the...

Synopsys Inc., a global leader providing software IP and services used to accelerate innovation in chips and electronic systems, presents Verdi3 I-2014.03 SP3 – is an advanced open platform for debugging digital designs with powerful technology that helps you comprehend complex and unfamiliar design behavior, automate difficult and tedious debug processes and unify diverse and complicated design environments. Synopsys Verdi3 I-2014.03 SP3 Verdi3 provides teams with a unified debugging solution for use across the entire heterogeneous verification environment. It supports a broad range of methodologies and languages used to design and verify complex SoCs. Its open architecture enables teams to use a single display format, sophisticated feature set, and unified waveform database whether they are using simulation engines from the...

Encounter Conformal ECO Designer ECO automation for greater predictability and design convergenceCadence® Encounter® Conformal® ECO Designer enables designers to implement RTL engineering change orders (ECOs) for pre- and post-mask layout, and offers early ECO prototyping capabilities for driving critical Yes/No project decisions.Engineering change orders (ECOs) have a wide variety of implementations that range from adding or removing logic in a design to more subtle changes such as cleaning up routing for signal integrity. All ECOs are focused on delivering products to market as fast as possible with minimal risk to correctness and schedule. ECOs can be a time of high stress, long work hours, and uncertainty. Even if the logic change is implemented in the netlist, there might not be...

Incisive Enterprise Simulator Multi-language simulation fuels testbench automation, low-power, metric driven verification, and mixed-signal verificationIncisive Enterprise Simulator (IES) provides the most comprehensive IEEE language support with unique capabilities supporting the intent, abstraction, and convergence needed to speed silicon realization. IES is the core engine for low-power verification working closely with Conformal LP, the digital engine for mixed-signal verification working with Virtuoso simulators, the testbench engine for simulation acceleration with Xtreme and Palladium, and the RTL engine working with TLM verification solutions.When digital simulation became commonplace in the 1980s, flows were simple: RTL, then gate, then implement. Since then, simulation has matured into verification and has become the critical means to enable productivity, predictability, and quality in complex FPGAs, ASICs, and...

Magillem Verification Scenarii New Magillem Verification Scenarii (MVS) Environment Configures Validation of IP & Sub-systems, and Automates Test Bench Generation Supports ARM cores integration and verification Single access mechanism to all resources of the design database for concurrent validation strategies Functional validation of large SOCs by multiple teams is significantly improved with IP XACT (IEEE1685) standard Paris, 25 October 2011,- MVS, Magillem Verification Scenarii, is the latest software proudly launched by Magillem , the leader of IP XACT based solutions for improved flow methodology : Complex SoCs require three layers of partitioning: functional sub systems with configurable parameters for architects, logical blocks (hierarchical assembly for implementation) used by designers and integrators, and functional validation subsets necessary for verification teams. MVS...

3D full-chip parasitic extraction and analysisCadence® Quantus™ QRC Extraction Solution is the industry’s fastest, most accurate parasitic extraction tool. Built with massively parallel technology and integrated with a field solver (Quantus FS), the solution delivers up to 5X faster signoff extraction for system-on-chip (SoC) and custom/analog designs. As a single, unified tool, Quantus QRC Extraction Solution supports both cell-level and transistor-level extractions during design implementation and signoff. The solution is fully certified for the 16nm FinFET process at TSMC. For better and faster design correlation and convergence, Quantus QRC Extraction Solution is seamlessly integrated with both Cadence Encounter® digital implementation and Cadence Virtuoso® custom design platforms. This integration supports in-design signoff methodology.product:cadence EXT (QRC Extraction)14.15 Lanaguage:english Platform:Linux32/Linux64 Size:2DVD

Encounter Conformal ECO Designer ECO automation for greater predictability and design convergenceCadence® Encounter® Conformal® ECO Designer enables designers to implement RTL engineering change orders (ECOs) for pre- and post-mask layout, and offers early ECO prototyping capabilities for driving critical Yes/No project decisions. Engineering change orders (ECOs) have a wide variety of implementations that range from adding or removing logic in a design to more subtle changes such as cleaning up routing for signal integrity. All ECOs are focused on delivering products to market as fast as possible with minimal risk to correctness and schedule. ECOs can be a time of high stress, long work hours, and uncertainty. Even if the logic change is implemented in the netlist, there might not...