Mentor.Graphics.Tessent.2015.4.Linux
Mentor.Graphics.Tessent.2015.4.Linux Instructor-led Training (Classroom and Live Online)Course Highlights After creating high-coverage test patterns utilizing Tessent® FastScan™ or Tessent® TestKompress®, the next step is to validate the patterns in a Verilog simulation environment to make sure that the patterns work in a timed simulation environment. The Verilog testbench created by Tessent Shell is run, and the simulation results are compared to the expected results from test pattern generation. Any mismatches that are identified must be solved prior to releasing the patterns. The Tessent ATPG Simulation Mismatch Debug class will teach you techniques for identifying the cause of these simulation mismatches. Debugging steps are defined, including understanding the Tessent Shell and Verilog simulation logfiles, how to identify the flip-flop and specific pattern...