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Installing TetraMAXThis section describes Synopsys license key requirements and the two types of installationfor TetraMAX ATPG and TetraMAX IddQTest, version B-2008.09.You can install TetraMAX as a stand-alone product or as an overlay product.• Stand-alone (txs)Install TetraMAX stand-alone in its own directory. The product ID for the stand-aloneversion is txs.• Overlay (tx)Install TetraMAX overlay in the same directory as the appropriate release of the synthesistools. See “Overlay Installation” The product ID for the overlay version is tx.Note:If you are going to install TetraMAX IddQTEST, you must install it first (see “OptionalInstallation of IddQTest”), then install TetraMAX ATPG as an overlay to the synthesis tools.License Key RequirementsTetraMAX version B-2008.09 uses the Synopsys Common Licensing (SCL) system. Forinformation about downloading SCL, installing SCL,...

::::::English Description:::::: Timing closure in today抯 advanced designs remains the number one challenge for designers today, especially at 90-nanometers (nm) and below. A trusted timing sign-off solution that accurately models and predicts silicon behavior is required to enable designers to quickly achieve timing closure. The PrimeTime STA SolutionThe Synopsys PrimeTime static timing analysis solution is the most trusted and advanced timing sign-off solution for gate-level designs. It is the industry抯 de-facto gold standard for gate-level static timing analysis and is a key component of the Galaxy?Design Platform. With a wide breadth of sign-off analysis capabilities, the PrimeTime STA solution provides a comprehensive and unmatched environment for timing sign-off and serves as an industry yardstick for timing analysis and sign-off. It...

OVAs provide language capabilities to build and reuse libraries of pre-built assertions. This macro capabilityprovides a mechanism to build a reusable library of assertions, which can be shared within groups or amongthe OpenVera community. With a library of assertions, designers will be able to reuse the prior specificationsand raise the level of abstraction of the specification.OVAs are part of the OpenVera open source standard. The open source model has been demonstrated toprovide a path for fast time to market with innovation and contribution from multiple sources.OVAs FeaturesOVAs are declarative with semantics that are formally based on the theories of regular expression and lineartemporal logic. These two theories provide a powerful combination for expressing common hardware activities,such as sequencing, invariants and...

Recent collaboration between UMC and Synopsys has resulted in a complete RTL-to-GDSII reference design flow, which now includes critical design for manufacturing features for UMC抯 90nm process. Suzanna Chang, Senior Director of Marketing for UMC, and Paul Lai, Group Manager of Strategic Alliances, Synopsys, explain how the use of this flow can help designers reduce design risk and speed time to results. UMC\’s Design for Manufacturing (DFM) efforts supplement the basic design work that is performed to support customers. This helps increase the chances of first time silicon success, which is critical in reducing time to market and overall costs at technologies of 90nm and below. Improved DFM solutions help customers realize enhanced yields, faster turnaround times, and reduced risk...

Synopsys’ Star-RCXT™ is the electronic design automation (EDA) industry’s gold standard forparasitic extraction. It provides a single solution for ASIC, system-on-chip (SoC), digital custom,memory and analog designs. Trusted by over 250 semiconductor companies and proven in thousandsof production designs, Star-RCXT delivers fast and sub-femtofarad accurate technology. The Star-RCXT solution offers advanced capabilities needed for sub-65-nanometer (nm) designs, includingvariation-aware parasitic extraction, chemical-mechanical polishing (CMP) based and litho-awareextraction, inductance extraction and analog mixed signal design flow. Its seamless integration withindustry leading physical verification, circuit simulation, timing, signal integrity, power, reliabilityand RTL2GDSII flows enables unmatched ease-of-use, increased productivity and reduced time-to-market. Star-RCXT is used by leading foundries to solve process modeling challenges at 65-nmand 45-nm.product:Synopsys Star-RCXT 2008.12 SP2 AMD64 Lanaguage:english Platform:Winxp/Win7 Size:138MB

Formality® is an equivalence-checking (EC) solution that uses formal, static techniques to determine if two versions of a design are functionally equivalent. The size and complexity of today’s designs, coupled with the challenges of meeting timing, area, power and schedule, requires that the newest, most advanced synthesis optimizations be fully verifiable. Formality supports all of the out-ofthe- box DC Ultra optimizations and so provides the highest quality of results that are fully verifiable. Formality supports verification of power-up and power-down states, multi-voltage, multi-supply and clock gated designs. Formality’s easy-to-use, flow-based graphical user interface and auto-setup mode helps even new users successfully complete verification in the shortest possible time.product:Synopsys Formality 2008.09 SP4 Linux Lanaguage:english Platform:Winxp/Win7 Size:55MB

::::::English Description:::::: The Formality® Equivalence Checker uses formal techniques to prove or disprove equivalence between two versions of the same design. Equivalence checking is a type of static analysis that verifies large designs both quickly and completely without the use of test vectors. The high performance and reduced risk of static analysis has led to the rapid adoption of equivalence checking within leading verification flows, making it a must for all competitive design processes.  Key Benefits共享软件资源网 Exhaustive verification, without test vectors, in a fraction of the time consumed by traditional dynamic techniques Proves functional correctness of register retiming, complex datapath, ECO, and low power implementations–from within a single product Reduces manual setup with verified automated setup guidance Verifies full-custom and...

Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today announced that Cypress Semiconductor Corp. has successfully taped out its West Bridge™ Antioch™ peripheral controller multimedia 3G/3.5G mobile phone integrated circuit (IC) using the Synopsys Galaxy™ design platform RTL-to- GDSII low-power solution, including the PrimeRail dynamic power network analysis solution. The multithreshold CMOS (MTCMOS) power gating feature in the Galaxy design platform enabled Cypress to complete its ultra-low-power design with world-class performance and optimized standby current. PrimeRail, a key component of the Galaxy design platform, enabled peak current analysis for the multiple power domains of the Power Gating-based design during physical implementation. \”For our mobile phone chip design, we needed a solution that could address peak current problems...

Simulates and analyzes systems, sub-systems and components (hydraulic, electronic, mechanical, thermal, etc.) under a variety of different operational and environmental conditions * Optimize system for performance, reliability, and cost * Reduce effects of variation * Bound worst case behavior * Repeatable processes – create 10,000s of virtual prototypes * Increase reliability for mechatronic systems, PCBs & wire harnesses * Implement Robust Design analyses such as stress, sensitivity, Monte Carlo, etc. * Quickly create a virtual system design * Reduce the need for physical prototypes * Increase model portability with language standards VHDL-AMS & MAST * Ensure accuracy by accessing a library of 30,000+ models * Create models quickly with model characterization tools * Protect intellectual property with model encryption *...

The Milkyway™ Database provides the unifying design storage for Synopsys?Galaxy™ Design Platform. The production-proven, widely used Milkyway database provides persistent data storage that links Galaxy platform tools together thereby eliminating the need for large, intermediate exchange files and preventing design intent loss through mismatched syntax of exchange formats. Milkyway is proven on well over 10,000 tape-outs including the latest 90 and 65 nanometer technology designs. Designed to be extensible, Milkyway is continuously augmented with new capabilities such as those required for signal integrity, power reduction, and yield enhancement. The Milkyway database C-API was opened for customer interfacing in 1998 and is available to 3rd parties at no charge through Synopsys MAP-in program.   Key Features and Benefits Production-proven database for...