Tags :Synopsys Page 8

SMC and Synopsys Collaborate to Validate Galaxy Custom Designer Solution with TSMC 28nm iPDK MOUNTAIN VIEW, Calif., June 9 /PRNewswire-FirstCall/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that it has collaborated with TSMC to validate Synopsys\’ custom design solution with TSMC\’s 28-nanometer (nm) interoperable process design kit (iPDK) and Analog/Mixed-Signal (AMS) Reference Flow 1.0. TSMC\’s 28nm reference phase-locked loop (PLL) design was used to validate Synopsys\’ comprehensive custom solution while demonstrating productivity-enhancing capabilities of the TSMC AMS Reference Flow 1.0. The validated solution from Synopsys includes the Galaxy Custom Designer® implementation, HSPICE® circuit simulation, CustomSim™ FastSPICE simulation, StarRC™ parasitic extraction and IC Validator physical verification solutions. Through...

The Synplify DSP tool provides a unique high-level synthesis methodology that realizes significant productivity and portability advantages. System and algorithm designers can quickly capture complex algorithmic behavior using the Synplify DSP library. The Synplify DSP synthesis engine allows designers to automatically implement and explore area/speed optimized RTL implementations from a single model. This eliminates the burden of hand-coding functions and architectural optimizations and results in significantly faster design capture, speeds time-to-market, and enables rapid design exploration for improved quality and lower cost.Product:Synopsys Synplify FPGA 2009.06 SP1 Linux Lanaguage:english Platform:Winxp/Win7 Size:516MB

Process and Device Simulation Tools Technology Computer-Aided Design (TCAD) refers to the use of computer simulations to develop and optimize semiconductor processing technologies and devices. Synopsys TCAD offers a comprehensive suite of products that includes industry leading process and device simulation tools, as well as a powerful GUI-driven simulation environment for managing simulation tasks and analyzing simulation results. The TCAD process and device simulation tools support a broad range of applications such as CMOS, power, memory, image sensors, solar cells, and analog/RF devices. In addition, Synopsys TCAD provides tools for interconnect modeling and extraction, providing critical parasitic information for optimizing chip performance.product:Synopsys Tcad Taurus Medici 2009.06 Linux64 Lanaguage:english Platform:Winxp/Win7 Size:89MB

Installing the SoftwareThe TCAD tools use the Synopsys Installer tool, which allows you to use agraphical user interface (GUI) or a text script. For information aboutdownloading Synopsys Installer and the TCAD tools, see Installing SynopsysTools, available at http://www.synopsys.com/install.To install the TCAD tools by EST or from the CD, follow the proceduresdescribed in Installing Synopsys Tools.Installing Synopsys Tools shows an example Synopsys media installation scriptfor the synthesis tools. The TCAD software is installed in a similar manner.The TCAD tools are stand-alone products and cannot be installed over otherexisting Synopsys products. You must create a new directory for each TCADproduct (such as Sentaurus, Taurus, Raphael NXT).Sentaurus can be installed in the same Sentaurus directory (STROOT) used forearlier Sentaurus releases (this is recommended)....

Saber Accelerates Robust Design Focus: Manage mechatronic complexity by accelerating Robust Design via simulation * Automotive (mid-class car) — 50+ microprocessors, 100+ sensors, 30+ electrical subsystems * Aerospace (A380) — 530km of wires, 100,000 cable sections, 40,300 connectors Results for OEMs and supply chain: * Optimize system for performance, reliability, and cost * Reduce effects of variation * Bound worst case behavior * Repeatable processes – create 10,000s of virtual prototypes * Saber * Key Benefits * Applications * Robust Design * Modeling * * Industries & Applications * Featuring the automotive and aerospace markets Automotive Robust Design solutions for vehicle power networks, in-vehicle networks (IVN) such as FlexRay, powertrain systems, and wire harness design & simulation.PDF DOWNLOAD DATASHEET Aerospace...

Library developers are facing increasing challenges at the 65nm and 45nm nodes, including increasing design rule complexity, time-to-market pressures, library richness, and late design rule changes. Manual layout is becoming increasingly impractical and expensive. The Cadabra® product offers a fully automated tool for the creation of standard cells layouts from SPICE netlists, and for migration of existing standard cell layouts to new design rules or architectures. With easy to use graphical interfaces and results that rival hand-crafted, the Cadabra product is the market leader in automated standard cell layout. Design Rule ComplexityWith advanced manufacturing processes, the number of design rules that must be enforced for each layer is increasing rapidly. Moreover, many of the newer design rules are complex rules...

Synopsys SOLD 2009.06帮助文档.这主要是galaxy_docs_2009.06. The Synopsys Online Documentation collection (SOLD) is for Synopsys Implementation Group products only. such as Design Compiler, IC Compiler, Formality, Power products, PrimeTime, Star-RCXT, and TetraMax.product:Synopsys SOLD 2009.06 Lanaguage:english Platform:Winxp/Win7 Size:3.68G

VCS® is the industry?s most comprehensive RTL verification solution in a single product, providing advanced bug-finding technologies, a built-in debug and visualization environment and support for all popular design and verification languages including Verilog, VHDL, SystemVerilog and SystemC™. The VCS solution?s advanced bug-finding technologies include full-featured Native Testbench, complete assertions and comprehensive code and functional coverage to find more bugs faster and easier. Additionally, the VCS Verification Library provides verification IP for today?s most popular bus standards. By natively integrating these technologies within its unique, single-compiler architecture, the VCS solution delivers up to 5X faster verification performance compared with using multiple, stand-alone tools. The VCS solution?s powerful debug and visualization environment minimizes the turnaround time to find and fix design...

VCS MX uses the Synopsys Installer tool, which allows you to use agraphical user interface (GUI) or a text script. For information aboutdownloading Synopsys Installer and VCS MX, see “Downloading theSoftware” in Installing Synopsys ToolsTo install VCS MX by EST or from the CD, follow the proceduresdescribed in Installing Synopsys ToolsExample 1-1 in Installing Synopsys Tools shows a Synopsys mediainstallation script for the synthesis tools. VCS MX is installed in a similarmanner.VCS MX is a stand-alone product and cannot be installed over an existingSynopsys product, including a prior version of VCS MX. You must createa new directory for VCS MX.Follow these steps.1. Set the VCS_HOME environment variable in the shell that you are usingin which the root_directory argument is the...

The ChallengeAccurate transistor-level analysis of crosstalk-delayAs designs go down to 90-nm and below, crosstalk-delay becomes more than 25%of total delay. Prior solutions including traditional static timing analysis with optional3rd party crosstalk delay analysis do not provide the accuracy and productivity thatis required. Concurrent timing and SI is a must to achieve silicon success.Full chip timing verificationTransistor- and gate-level static timing analysis need to work together to achievefull chip timing verification (i.e) a seamless and accurate timing analysis flowfrom custom design to gate-level with PrimeTime is required. To achieve higherproductivity, NanoTime has the same commands as PrimeTime whenever theyare applicable.Concurrent timing and signal-integrity (SI) analysis provides higherpredictability and better productivityover existing solutions. NanoTimeoffers integrated timing and crosstalk-delay analysis to achieve higher...