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::::::English Description:::::: Synopsys’ Leda® 2007.03 is a programmable design and coding guideline checker that delivers full chip mixed-language (Verilog and VHDL) and mixed representation (RTL & gate) capabilities to speed development of complex system-on-chip (SoC) designs. Leda抯 pre-packaged rules greatly enhance a designer’s ability to check HDL code for synthesizability, simulatability, testability, reusability, and RTL/gate signoff. Leda detects clock synchronization-related bugs, isolates hard-to-time circuits, verifies layout considerations and improves DFT for higher ATPG coverage. Leda comes prepackaged with rules to improve performance of Synopsys tools, such as VCS MX, DC and Formality.   Key Benefits Finds complex bugs, such as those associated with multiple clock domains using static analysis Verifies consistency of design and SDC constraints for DC, PrimeTime and Astro...

The DesignWare Library provides a comprehensive portfolio of synthesizable and verification IP including an AMBA-based on-chip bus solution, memory IP, popular processor cores, bus and I/O standards, and performance enhancing datapath IP elements. The following product documentation is for the DesignWare Library\’s synthesizable and verification IP components. You can access product documentation for the DesignWare digital and mixed-signal IP cores using the “Search for IP” box in the upper right hand corner of this page.product:Synopsys DesignWare.vip Smartmodels 2005.09 Lanaguage:english Platform:Winxp/Win7 Size:101MB

Synopsys, Inc. (Nasdaq:SNPS), a world leader in semiconductor design software, announced the availability of advanced device parameter measurement functionality in its Hercules(TM) Physical Verification Suite (PVS). Developed to support the latest release of 65-nanometer (nm) design kits from IBM (NYSE: IBM), this new functionality enables IBM foundry customers using the Hercules layout versus schematic (LVS) rule files in the kit to easily and accurately correlate device behavior to the IBM process. These IBM foundry customers also have access to the latest Hercules design rule checking (DRC) as part of the 65 nm design kit release. These files are qualified for accuracy and optimized for performance. “We have been supporting Synopsys Hercules PVS for over a decade,” said Dave Harame, director...

>::::::English Description:::::: Raphael is the gold standard, 2D and 3D resistance, capacitance, and inductance extraction tool for optimizing multi-level interconnect structures and on-chip parasitics in small cells. As a reference field solver, Raphael provides the most accurate parasitic models in the industry. Trusted by major foundries, interconnect parasitics generated by Raphael are included as part of their design reference guide. Benefits Analyze complex on-chip interconnect structures and the influence of process variation Create a parasitic database for both foundries and designers to study the effect of design rule change Generate accurate capacitance rules for layout parameter extraction (LPE) tools product:Synopsys Raphael 2006.12 Linux Lanaguage:english Platform:Winxp/Win7 Size:36MB

FEATURED TECHNOLOGY CustomSim Circuit SimulationUnified AMS verification technologies deliver 4x performance improvement VCS Multicore Technology2x verification speed-up on complex designs Lynx Design SystemThe Lynx Design System is a highly automated, production-ready, chip implementation platform. Power-Aware TestBreakthrough technology in DFT MAX compression and TetraMAX ATPG. SuperSpeed USB 3.0Learn about USB 2.0 vs. 3.0 and how to evaluate a USB IP solution.product:Synopsys Circuit Explorer 2006.03 Linux Lanaguage:english Platform:Winxp/Win7 Size:62MB

::::::English Description:::::: FPGA Compiler II Release Notes ——————————————————————————– These release notes present the latest information about FPGA Compiler II version T-2003.09 FC3.8 in the following sections: New Features, Enhancements, and Changes Resolved STARs For information about earlier releases of FPGA Compiler II, log on to SolvNet. To access SolvNet, Go to the SolvNet Web page at http://solvnet.synopsys.com. If prompted, enter your user name and password. (If you do not have a Synopsys user name and password, follow the instructions to register with SolvNet.) Click Release Notes in the column on the left side of the SolvNet Web page. New Features, Enhancements, and Changes FPGA Compiler II version T-2003.09 FC3.8 provides new features, enhancements, and changes as described in the following...

NanoSim™, an advanced circuit simulator for memory and mixed-signal verification, combines best-in-class simulation technologies from TimeMill® and PowerMill® to deliver an unparalleled combination of timing and power analysis and diagnostics in a single tool.product:Synopsys NanoSim 2006.06 Lanaguage:english Platform:Winxp/Win7 Size:569MB

::::::English Description:::::: Synopsys Technology Computer Aided Design (TCAD) offers a comprehensive suite of products that includes the industry leading process and device simulation tools, as well as a powerful GUI-driven simulation environment for managing simulation tasks and analyzing simulation results. The Synopsys TCAD process and device simulation tools support a broad range of applications such as CMOS, power, memory, optoelectronics, analog/RF and laser. In addition, Synopsys TCAD provides tools for interconnect modeling and extraction, providing critical parasitic information for optimizing chip performance. TCAD for Manufacturing (TFM)The Sentaurus TFM suite, which includes PCM Studio and PCM Library, provides a powerful environment for capturing multivariate process杁evice朿ircuit relationships in process compact models (PCMs), allowing a fast turnaround for identifying and analyzing factors that...

PathMill  is a leading-edge, industry-proven static timing analysis tool for block and full-chip timing verification. PathMill enables the custom and system-on-chip (SoC) designer to quickly detect and correct design flaws and timing . ::::::English Description:::::: PathMill  is a leading-edge, industry-proven static timing analysis tool for block and full-chip timing verification. PathMill enables the custom and system-on-chip (SoC) designer to quickly detect and correct design flaws and timingproduct:Synopsys Pathmill 2006.12 Linux Lanaguage:english Platform:Winxp/Win7 Size:47MB

Synopsys AURORA 2007.03 Linux is a complete semiconductor device characterization and parameter extraction system, providing capabilities to measure device characteristics, extract circuit-level model parameters from measured or simulated data, and analyze results graphically. product:Synopsys AURORA 2007.03 Linux Lanaguage:english Platform:Winxp/Win7 Size:78MB