Tags :Synopsys Page 12

Synopsys公司发布的针对65nm 和 45nm 设计的电子类软件cadabra。   ::::::English Description:::::: Library developers are facing increasing challenges at the 65nm and 45nm nodes, including increasing design rule complexity, time-to-market pressures, library richness, and late design rule changes. Manual layout is becoming increasingly impractical and expensive. The Cadabra® product offers a fully automated tool for the creation of standard cells layouts from SPICE netlists, and for migration of existing standard cell layouts to new design rules or architectures. With easy to use graphical interfaces and results that rival hand-crafted, the Cadabra product is the market leader in automated standard cell layout. Design Rule ComplexityWith advanced manufacturing processes, the number of design rules that must be enforced for each layer is increasing rapidly. Moreover, many of the newer...

OverviewToday’s complex integrated circuit (IC) designs generate a vast amount of simulation data. CosmosScope™ turns that mountain of data into useful information. With powerful analysis and measurement capabilities, patented waveform-calculator technology, and scripting language based on the industry standard Tcl/Tk, CosmosScope offers unparalleled capability and flexibility to analyze design performance and ensure design quality. CosmosScope supports all Synopsys simulators: HSPICE®, NanoSim™, Saber® and SaberHDL. CosmosScope benefits * Supports all Synopsys simulation products with a single viewer including HSPICE, NanoSim Saber, and SaberHDL * Provides powerful Tcl/Tk-based scripting language for easy customization * Performs post-processing of analog and digital simulation results * Automatically annotates graphs with design information using true WYSIWYG graphics, including arrows, shapes and text * Annotates graphs with...

As technology feature sizes shrink, conductors get smaller, and supply voltages reduce, the corresponding current per scaled feature size increases exponentially. These changes cause power-rail IR (voltage) drop and electromigration (EM) effects that significantly degrade performance and might cause the circuit to malfunction. To eliminate such problems, Astro-Rail™ provides an accurate and design-stage comprehensive sign-off solution for power consumption, IR drop and EM analysis for advanced-technology designs. Astro-Rail is an important component of Synopsys?Milkyway™-based Galaxy™ solution. Using Synopsys?proprietary Dynamic-Macromodeling™ technology, Astro-Rail assists in reducing time to market and ensures reliability. In Astro-Rail, IR drop and EM analysis of million gate designs are completed in minutes. Astro-Rail provides sign-off quality analysis results within five percent tolerance of HSPICE® with Star-RCXT™ parasitic...

:::::English Description::::::Synopsys?JupiterXT™ design planning solution enables fast feasibility analysis for a preview of implementation results, and provides detailed floor planning capabilities for flat or hierarchical physical design implementation styles. Project leaders and physical designers of ASIC or COT designs benefit from the accurate prediction and production-proven convergence JupiterXT provides. Feasibility analysis is supported for incomplete netlists in the form of black boxes or early gate level netlists. Powerful placement algorithms incorporate designers?knowledge of black box content and produce routable floorplan results using autoshaping with full rectilinear support. If gate netlists are available, the placement algorithms apply a virtual flat approach that places hard macros and standard cells simultaneously. As more detailed design content is added to netlists as a result...

Synopsys, Inc. today announced that UMC has adopted Synopsys TetraMAX diagnostics to accelerate yield learning for designs that utilize the Synopsys DFT MAX scan compression automation solution. Rapid yield learning depends on the accuracy and efficiency of failure analysis, a manually intensive and time-consuming process of identifying the individual circuit in a design that could cause a device to fail. Using Synopsys TetraMAX diagnostics to perform this task automatically on DFT MAX-compressed scan patterns, UMC engineers were able to substantially decrease the time and effort required for failure analysis. \”As part of UMC\’s leading-edge manufacturing products and services, we are continuing to build upon our portfolio of robust rapid learning tools,\” said S. R. Sheu, Product Engineering Director at UMC....

ynopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today announced that Cypress Semiconductor Corp. has successfully taped out its West Bridge™ Antioch™ peripheral controller multimedia 3G/3.5G mobile phone integrated circuit (IC) using the Synopsys Galaxy™ design platform RTL-to- GDSII low-power solution, including the PrimeRail dynamic power network analysis solution. The multithreshold CMOS (MTCMOS) power gating feature in the Galaxy design platform enabled Cypress to complete its ultra-low-power design with world-class performance and optimized standby current. PrimeRail, a key component of the Galaxy design platform, enabled peak current analysis for the multiple power domains of the Power Gating-based design during physical implementation. \”For our mobile phone chip design, we needed a solution that could address peak current problems...

::::::English Description:::::: HSIMplusHSIMplus™ 2007.03 Linux is a fully-integrated suite of tools for the design and verification of nanometer ICs, built upon the production-proven HSIM hierarchical Fast-SPICE simulator. HSIMplus exceeds the capabilities of competitor’s Fast-SPICE simulators, by providing a complete solution for analysis of the effects that dominate performance and reliability in silicon at 90nm and 65nm process nodes. HSIM® delivers superior performance and capacity over traditional SPICE-based simulators, by applying two innovative and proprietary techniques: Hierarchical Storage and Isomorphic Matching   Hierarchical StorageTraditional SPICE-based simulators employ matrix-solving algorithms that must flatten the hierarchy that designers build into their circuit, in order to simultaneously solve for all node voltages and branch currents at every time step in a simulation. The hierarchical solver...

:::::: HSIMplusHSIMplus™ 2007.03 is a fully-integrated suite of tools for the design and verification of nanometer ICs, built upon the production-proven HSIM hierarchical Fast-SPICE simulator. HSIMplus exceeds the capabilities of competitor’s Fast-SPICE simulators, by providing a complete solution for analysis of the effects that dominate performance and reliability in silicon at 90nm and 65nm process nodes. HSIM® delivers superior performance and capacity over traditional SPICE-based simulators, by applying two innovative and proprietary techniques: Hierarchical Storage and Isomorphic Matching   Hierarchical StorageTraditional SPICE-based simulators employ matrix-solving algorithms that must flatten the hierarchy that designers build into their circuit, in order to simultaneously solve for all node voltages and branch currents at every time step in a simulation. The hierarchical solver in HSIM...

。Complete and accurate cell characterization is essential for automated implementation and verification of complex system-on-chips (SoC). Capturing sufficiently accurate timing, power and signal integrity information, as well as operating condition variability for 90-nm and 65-nm technologies requires major additions to the technology information developed for previous technologies. Synopsys?NanoChar characterization system is a complete, automated, characterization solution for standard cells and other macrocells that delivers the accuracy and capabilities required for 90-nm and below process geometries.Working in conjunction with Synopsys?highly-accurate HSPICE circuit simulator, NanoChar characterization system derives critical timing, power, and signal integrity data to create open, industry-standard Liberty (.lib) and Verilog (.v) files for use by all Synopsys tools as well as other EDA tools. The NanoChar characterization system lowers...

Synopsys Saberproduct:Synopsys Saber 2007.03 linux Lanaguage:english Platform:Winxp/Win7 Size:392MB