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TetraMAX® ATPG automatically generates high quality manufacturing test patterns. It\’s the only ATPG solution optimized for a wide range of test methodologies and integrated with Synopsys\’ patented DFTMAX™ compression the leading test synthesis tool. The unparalleled ease-of-use and high performance provided by TetraMAX ATPG allows RTL designers to quickly create efficient, compact tests for even the most complex designs. PDFDownload Datasheet Key Benefits * Increases product quality with power-aware test patterns for high defect detection * Reduces testing costs through the use of advanced pattern compaction techniques * Increases designer productivity by leveraging integration with Synopsys DFTMAX compression * Creates tests for complex and multi-million gate designs Features * Extremely high capacity and performance * Multicore support for accelerated run...

Current ActivitiesAs an extension of the worldwide VERA R&D team, the Synopsys India VERA group is responsible for the development of standalone VERA tools and enhancements to the VERA language. It is also involved in various VERA integration projects including those with third party tools. The team\’s mission is centered on making ongoing key R&D contributions to the VERA product. Job ResponsibilitiesThe VERA R&D team works on technologies and products in the area of functional verification. Specific projects include design and development in: compilers, data structures, algorithms in support of the VERA runtime library, interfaces between VERA and 3rd party simulation tools, and GUIs. Job RequirementsAn ideal candidate desirous of working in this area should have experience in developing and...

The third product in the process-aware design-for-manufacturing (PA-DFM) family is Fammos; the first special-purpose TCAD PA-DFM tool that analyzes stress evolution for the entire fabrication process of interconnects. Fammos performs 3D backend process simulations using design database and process recipes. With specialized algorithms for fast 3D structure construction, mesh generation, and equation solving, Fammos predicts interconnect stress distributions from multiple stress sources and accounts for proximity effects. Combining the best-in-class capabilities from Synopsys, Fammos is capable of detecting stress hot spots that are susceptible to debonding, voiding and cracking. It employs a set of physics-based models to evaluate reliability failures. Using the Sentaurus Workbench user interface, Fammos will facilitate technology explorations with parameterized input files and scheduled run splits. Benefits...

Sentaurus Process is an advanced 1D, 2D, and 3D process simulator for developing and optimizing silicon and compound semiconductor process technologies. Created by combining the best-in-class features from Synopsys and former ISE TCAD products, together with a wide range of new features and capabilities, Sentaurus Process is a new-generation process simulator for addressing the challenges found in current and future process technologies. Equipped with a set of advanced process models, which include default parameters calibrated with data from equipment vendors, Sentaurus Process provides a predictive framework for simulating a broad range of technologies from nanoscale CMOS to large-scale high-voltage power devices. Sentaurus Process is part of the comprehensive Synopsys suite of core TCAD products for multidimensional process, device, and system...

::::::English Description::::::  HSPICE is the industry s gold standard for accurate circuit simulation and offers foundry-certified MOS device models with state-of-the-art simulation and analysis algorithms. With over 25 years of successful design tapeouts, HSPICE is the industry s most trusted and comprehensive circuit simulator. Design ChallengesAs IC geometries continue to shrink, the need for an accurate circuit simulator is critical. Designers require a highly accurate circuit simulator to precisely predict the timing, power consumption, functionality, and yield of their designs. As board and package speeds increase, designers need to employ increasingly accurate signal integrity analysis. SolutionHSPICE <!– Key Benefits –> Accuracy Gold standard for accurate circuit simulation. Extensive model support of the most accurate and expansive set of industry-standard and...

::English Description:::::: TetraMAX® ATPG automatically generates high quality manufacturing test vectors. TetraMAX is the only ATPG solution optimized for a wide range of test methodologies that抯 integrated with Synopsys?DFT MAX, the leading test synthesis tool. The unparalleled ease-of-use and high performance provided by TetraMAX allows RTL designers to quickly create efficient, compact tests for even the most complex designs. Key Benefits Increases product quality with generated test vectors for high defect detection Reduces testing costs through the use of advanced vector compaction techniques Increases designer productivity by leveraging integration with Synopsys DFT MAX Creates tests for complex and multi-million gate designs Key Features Extremely high capacity and performance Integrated graphical user interface Integrated simulation waveform viewer Integrated context-sensitive online help...

Installing the Software by ESTDownload the CosmosScope release to a temporary directory. You can obtainthe latest CosmosScope download instructions from the SolvNet ReleaseLibrary.To install the software on UNIX systems,1. Double-click the downloaded file, or enter the file name at the commandprompt. For example,% CosmosScope_version_platform.binwhere version is the release you are installing. Replace platform with theappropriate platform keyword (see Table 1 on page 5).2. Continue with the steps in Installing Synopsys Tools.To install the software on Windows systems,1. Locate and double-click the .exe file. For example, double-clickCosmosScope_version_win.exewhere version is the release you are installing.2. Continue with the steps in Installing Synopsys Tools.product:Synopsys Cosmos-Scope 2007.03 SP1 Win Lanaguage:english Platform:Winxp/Win7 Size:66MB

:::::English Description:::::: Innovator is a powerful, fully integrated tool environment for developing, running and debugging virtual platforms. It comes with full SystemC™ (IEEE 1666) support. Its main components are: Schematic system editor, to instantiate, configure and connect IP model components to rapidly build Virtual Platforms Language Editor, to interactively describe behavior of hardware component using a combination of graphical system constructs and ANSI C and SystemC Design Browsers, to quickly reconfigure IP components, to edit run-time scripts and to explore the system connectivity Library Manager, to manage and explore re-usable model libraries Code Generation, to generate optimized C++ code for the graphical language front-end and to seamlessly invoke host compilers to compile the Virtual Platform Hardware debugger, to take run-time...

::::::English Description:::::: IC WorkBench (ICWB) is a powerful, hierarchical layout visualization and analysis tool with GDSII/OASIS viewing, layout editing, and high-speed lithography simulation and analysis. IC WorkBench is designed to address a variety of lithographic applications including: Mask Synthesis flow development, OPC model development and calibration, lithography verification error analysis,design rule creation and validation, yield and printability optimization of critical cells, and new process development.IC WorkBench provides qualitative and quantitative information on wafer imaging characteristicsunder varying parameter and process conditions. High Speed, High Capacity Viewing and EditingICWB builds on a solid foundation of fast GDSII/OASIS viewing and editing tool designed to handle the geometrically increasing file sizes of advanced process nodes. ICWB loads gigabytes of data in minutes and has...

::::::English Description:::::: Synopsys?TechXpress™ products enable a revolutionary amount of process insight in a minimum amount of silicon area that is not possible with conventional characterization technologies. A decade of experience in leading-edge technology development and yield optimization has shaped the TechXpress product line to enable the types and volumes of information that are required for successful nanometer-era technology development. Solutions Span Entire Semiconductor Process Life Cycle TechXpress solutions span the entire semiconductor process life cycle. Solutions are grouped into four chip sets that are used by process integration and yield engineers to target the specific tasks found at each stage of the process life cycle. The chips sets are classified as, ToolBox (for early materials and litho characterization), RaceTrack (for...