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::::English Description:::::: Timing closure in today advanced designs remains the number one challenge for designers today, especially at 90-nanometers (nm) and below. A trusted timing sign-off solution that accurately models and predicts silicon behavior is required to enable designers to quickly achieve timing closure. The Synopsys PrimeTime static timing analysis solution is the most trusted and advanced timing sign-off solution for gate-level designs. It is the industry de-facto gold standard for gate-level static timing analysis and is a key component of the Galaxy?Design Platform. With a wide breadth of sign-off analysis capabilities, the PrimeTime STA solution provides a comprehensive and unmatched environment for timing sign-off and serves as an industry yardstick for timing analysis and sign-off. It delivers to designers...

High-Level Algorithm Implementation for FPGAs and ASICs The Synplify DSP tool provides a unique high-level synthesis methodology that realizes significant productivity and portability advantages. System and algorithm designers can quickly capture complex algorithmic behavior using the Synplify DSP library. The Synplify DSP synthesis engine allows designers to automatically implement and explore area/speed optimized RTL implementations from a single model. This eliminates the burden of hand-coding functions and architectural optimizations and results in significantly faster design capture, speeds time-to-market, and enables rapid design exploration for improved quality and lower cost.product:Synopsys Synthesis Tools 2008.09 SP2 AMD64 Lanaguage:english Platform:Winxp/Win7 Size:277MB

* Rapidly create and verify technology independent DSP models that are fully portable across vendor and device technologies. * Unique Synplify DSP synthesis engine automatically creates optimized algorithm RTL architectures from your DSP model. * Powerful DSP synthesis optimizations enable exploration of speed/area/device technology tradeoffs without changing your DSP model or verification. * Comprehensive DSP library with full multi-rate support and advanced fixed-pint quantization analysis. * M-Control feature enables use of M-language for concise expression of complex state machine and control logic functionality. * Vector support enables concise expression of parallel and multi-channel algorithms common in wireless and video applications.product:Synopsys Synthesis Tools 2008.09 SP2 Linux Lanaguage:english Platform:Winxp/Win7 Size:268MB

ynopsys, Inc. is the solutions leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/ . NOTE: Synopsys is a registered trademark and Magellan is a trademark of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their...

The installation instructions in this document are the most up-to-dateavailable at the time of production. However, changes might have occurred.For the latest installation information, see the product release notes ordocumentation.This document provides instructions for the UNIX, Linux, and Windowsplatforms. The document includes the following sections:Preparing for InstallationInstalling SpiceExplorer and WaveView Analyzer (UNIX and Windows)Invoking SpiceExplorer and WaveView Analyzer on WindowsInstalling the SX-CDS Link PackageInstalling the SX-DAIC Link PackageInstalling the SX-VSDE Link PackageViewing and Printing SpiceExplorer and WaveView AnalyzerDocumentation in Portable Document Format (PDF)Troubleshooting SpiceExplorer and WaveView Analyzer Installation onSolaris PlatformsUninstalling SpiceExplorer and WaveView AnalyzerCustomer Supportproduct:Synopsys SpiceExplorer 2008.03 SP1 Linux Lanaguage:english Platform:Winxp/Win7 Size:54MB

Synopsys Analysis and Debug products provide a unique approach to transistor-level verification that enables engineers to efficiently analyze and debug complex AMS systems-on-chips (SoCs). CustomExplorer addresses the need for an effective transistor-level debugging environment. The tools provide a netlist-driven debugging and visualization modules, and Custom WaveView with ACE scripting option completes the package. The environment provides front-to-back productivity solutions to speedup verification cycle and reduces total design cost.product:Synopsys SpiceExplorer 2008.09 Win Lanaguage:english Platform:Winxp/Win7 Size:9MB

Synopsys\’ Leda® is a programmable design and coding guideline checker that delivers full chip mixed-language (Verilog and VHDL) and mixed representation (RTL & gate) capabilities to speed development of complex system-on-chip (SoC) designs. Leda’s pre-packaged rules greatly enhance a designer\’s ability to check HDL code for synthesizability, simulatability, testability, reusability, and RTL/gate signoff. Leda detects clock synchronization-related bugs, isolates hard-to-time circuits, verifies layout considerations and improves DFT for higher ATPG coverage. Leda comes prepackaged with rules to improve performance of Synopsys tools, such as VCS MX, DC and Formality. Key Benefits * Finds complex bugs, such as those associated with multiple clock domains using static analysis * Verifies consistency of design and SDC constraints for DC, PrimeTime and Astro *...

OverviewWith process geometries reaching90-nanometers (nm) and below, thereare many nanometer effects that canimpact timing. Accurate analysis ofthese effects is required to identify realtiming issues.Synopsys’ NanoTime tool is thenext-generation transistor-levelstatic timing analysis solution thataddresses the emerging challengesin signal integrity (SI) analysisassociated with custom designs.NanoTime offers concurrent timingand SI analysis, accuracy withinfive percent of HSPICE®, and theperformance required to analyzecomplex transistor circuits overnight.Its seamless integration with Synopsys’PrimeTime® product enables full-chipanalysis of designs that includes bothgate- and transistor-level blocks.NanoTime is a key component of theSynopsys custom design verificationsolution that includes CustomSim®and HSPICE for circuit simulationand ESP-CV for symbolic simulation.product:Synopsys Nanotime 2007.12 SP2 Linux Lanaguage:english Platform:Winxp/Win7 Size:81MB

The Milkyway™ Database provides the unifying design storage for Synopsys’ Galaxy™ Design Platform. The production-proven, widely used Milkyway database provides persistent data storage that links Galaxy platform tools together thereby eliminating the need for large, intermediate exchange files and preventing design intent loss through mismatched syntax of exchange formats. Milkyway is proven on well over 10,000 tape-outs including the latest 90 and 65 nanometer technology designs. Designed to be extensible, Milkyway is continuously augmented with new capabilities such as those required for signal integrity, power reduction, and yield enhancement. The Milkyway database C-API was opened for customer interfacing in 1998 and is available to 3rd parties at no charge through Synopsys\’ MAP-in program. Key Features and Benefits * Production-proven database...

Synplicity’s Synplify Premier Linux software is the ultimate FPGA timing closure and debug solution. It builds upon Synplicity’s industry-leading synthesis technology by adding graph-based physical synthesis and real-time simulator-like visibility into operating FPGA devices. The Synplify Premier tool’s graph-based physical synthesis technology addresses timing closure by merging optimization, placement, routing and generates a fully placed and physically optimized design ready for final routing using the FPGA vendor routing tool. The highly accurate correlation between the Synplify Premier product’s timing estimates and final design timing enables more aggressive optimization resulting in improved device performance. In addition, the Synplify Premier product offers FPGA Designers and ASIC Prototypers the most efficient method of in-system verification of FPGAs. The Synplify Premier software dramatically accelerates...