Aldec Riviera-PRO 2009.02
Aldec, Inc., announced today the release of Riviera-PRO 2008.06, a behavioral, structural and mixed HDL language simulator for multi-million gate ASIC and FPGA designs. Riviera-PRO 2008.06 includes Verilog® simulation performance enhancements, increased SystemVerilog support, seamless SystemC/C/C++ and HDL co-debugging in common environment and new support for SVA and PSL assertions in the Waveform Viewer. Riviera-PRO supports System Level Verification with SystemC and SystemVerilog, Assertions based verification, Open Verification Methodology (OVM), Electronic System Level (ESL) and STARC® based Linting. Verilog Simulation Performance Speed-upVerilog simulation speed at the gate level has been increased up to 2.3X over the previous release. Memory allocation during simulation has been significantly reduced, to enable larger solutions on 32 and 64 bit platforms. All mixed language designs...