Tags :ModelSIM.SE.v10.1c

ModelSimASIC and FPGA designView Detail Mentor Graphics was the first to combine single kernel simulator (SKS) technology with a unified debug environment for Verilog, VHDL, and SystemC. The combination of industry-leading, native SKS performance with the best integrated debug and analysis environment make ModelSim® the simulator of choice for both ASIC and FPGA designs. The best standards and platform support in the industry make it easy to adopt in the majority of process and tool flows.Overview Unified mixed language simulation engine for the fastest regression suite throughput Native support of Verilog, SystemVerilog for design, VHDL, and SystemC for effective verification of the most sophisticated design environments Fast time-to-debug causality tracing and multi-language debug environment Advanced code coverage and analysis tools...