Tags :Mentor Graphics Page 18

ICX® and ICX Pro provide an intuitive user interface for engineers to explore signal integrity solutions in their high-speed designs. Engineers learning signal integrity are offered a concise view of how things work, while those more seasoned are able to investigate signal integrity effects in their designs in great detail. Components are modeled using industry standard IBIS models, with support for virtually all IC model types, while simulations are provided by our proven ICX simulation technology. With a library of default IBIS models provided, engineers can begin evaluating high-speed design solutions easily and quickly. The Tau® board-level symbolic timing analysis tool performs comprehensive worst-case timing analysis and verification on designs using an advanced symbolic timing methodology, eliminating false paths that...

::::::English Description:::::: Catapult is for ASIC and FPGA hardware designers of portable wireless, video, and image processing equipment who need to deliver optimal implementations with aggressive time-to-market requirements. Catapult is a high-level synthesis tool that uses industry-standard ANSI C++ to generate correct-by-construction, high-quality RTL 10-100x faster than other methods. Unlike traditional RTL design methodologies, Catapult enables the designer to pick the best architecture for given performance/area/power requirement and avoids the design errors introduced from hand coding the RTL description. product:Mentor Graphics Catapult Synthesis 2007b ESL Lanaguage:english Platform:Winxp/Win7 Size:110MB

Mentor Graphics TPD translators能够提供PCB 文件和 从Cadstar, OrCad, PCAD or Protel 的footprint libraries到PADS的转换。 ::::::English Description:::::: Mentor Graphics TPD translators Provides translation for PCB Layout files and footprint libraries from Cadstar, OrCad, PCAD or Protel to PADS Layout. product:Mentor Graphics TPD translators Lanaguage:english Platform:Winxp/Win7 Size:26MB

::::::English Description::::::  Mentor Graphics PADS Layout to Expedition Translators 2007  enable PADS files to Expedition files.product:Mentor.Graphics PEX 2007 Lanaguage:english Platform:Winxp/Win7 Size:25MB

::::::English Description:::::: Mentor Graphics I/O Designer provides bi-directional integration, data management and the ability to perform concurrent design of your FPGA and PCB. Focused on optimizing system performance, designer productivity and reducing product manufacturing costs, I/O Designer eliminates the barriers between FPGA and PCB flows and design organizations.product:Mentor Graphics I/O Designer 7.2 Linux HDL Lanaguage:english Platform:Winxp/Win7 Size:94MB

Mentor Graphics Vendor-Independent Flow 2006-IND2006 Linux 完整的PCB设计解决方案，包含具有强大功能的布局和模拟工具的概略图定义 ::::::English Description:::::: Mentor Graphics Announces Precision RTL Plus for FPGA Synthesis – Vendor-Independent Flow 2006 Linux(IND2006)  New Features for IND2006 ICX The following are the new features for ICX 3.6.0-ICX Pro simulator  -ICX Pro Waveform Analyzer with FFT   -Allegro 15.5 interface support  -Support for ndd-files with long property values I/O Designer-Concurrent design of FPGA and PCB through bi-directional communication between FPGA and PCB design environments-Optimize FPGA pin assignments for PCB routing and system performance  -Automatic symbol generation and fracturing  -I/O design data management  -FPGA constraints verification including Timing constraints  -Configurable power and ground PCB signal names -View of layout placement for I/O optimization –Automatic unravel nets  -Mapping between HDL and PCB signal names  -Import...

>::::::English Description:::::: Mentor Graphics Announces Precision RTL Plus for FPGA Synthesis – Vendor-Independent Flow 2006(IND2006)  New Features for IND2006 ICX The following are the new features for ICX 3.6.0-ICX Pro simulator  -ICX Pro Waveform Analyzer with FFT   -Allegro 15.5 interface support  -Support for ndd-files with long property values I/O Designer-Concurrent design of FPGA and PCB through bi-directional communication between FPGA and PCB design environments-Optimize FPGA pin assignments for PCB routing and system performance  -Automatic symbol generation and fracturing  -I/O design data management  -FPGA constraints verification including Timing constraints  -Configurable power and ground PCB signal names -View of layout placement for I/O optimization –Automatic unravel nets  -Mapping between HDL and PCB signal names  -Import PCB design wizard  -Full synchronisation wizard  -DMS corporate...

RTL (Front End) ToolsProduct DescriptionPlatform Express™, Mentor Graphics’ platform-based design product, enables design creation and verification by automating IP reuse. The product documents all aspects of IP using the IP-XACT™ XML databook format provided through The SPIRIT Consortium. The IP-XACT specification uses XML to create a machine-interpretable IP databook; it includes design information that software tools then use to automatically configure and integrate an IP block into a design. The power of IP-XACT is accessed through generators, which are programs that interpret the IP-XACT data to create design data. Platform Express comes with some of the most sophisticated generators available. These include mixed-language VHDL and Verilog generators that create ready-to-synthesize designs to work on a range of simulators, documentation generators,...

Seamless為MentorGraphic提供的硬體/軟體協同驗證工具，提供高效能和高準確性的軟硬體虛擬平台混合驗證，能降低整合性錯誤的風險並加快產品上市的速度，seamless支擁有業界最大的協同驗證模型資料庫，包括嵌入式設計最常使用的所有架構，而每個 Seamless處理器模組包含一個指令集模擬器，能夠執行組合語言碼和除錯,並提供處理器中的暫存器叢集所有的控制和觀察， Seamless 並有記憶體最佳化技術的專利，這個技術在嵌入式軟體的執行上提供速度上的提昇，並使邏輯模擬器有詳細分析和除錯的功能，配合這些特性 Seamless 可將單晶片系統的測試從硬體雛型系統轉換到虛擬的雛型系統，因此可輕易的更改軟硬體模組，在投入硬體前就能確保軟硬體介面的準確性，大幅的縮短了設計的時程。 Seamless CVE是Mentor Graphics推出的嵌入式系统软/硬件协同验证解决方案。通常，嵌入式软件的开发会滞后于硬件开发，特别是软/硬件的集成调试，必须等到物理原型生产出来以后。所以无法在设计的早期发现软/硬件接口之间的问题。一旦硬件原型有错，修改后还必须从新生产，然后再进行调试。整个设计过程排错困难，周期长，投入高。Seamless CVE将嵌入式软件开发工具和逻辑仿真器结合起来，使项目开发小组在物理原型（电路板或芯片）生产出来之前，就能够使用同一个系统模型进行高性能的软/硬件协同验证，使软件和硬件开发成为并行的过程，从而及早发现并改正软/硬件接口中的错误，缩短设计周期，减少投入。Seamless CVE还可以按照用户的配置来运行，使设计人员既能在需要时观测到所有的软/硬件交互细节，也能通过不同的优化策略来加速软件代码的执行，提高协同验证的效率。　主要特点：　→　缩短嵌入式系统（板上系统和片上系统）的开发周期。　→　减少硬件原型的设计反复次数。　→　加速设备驱动程序和硬件诊断程序的调试。　→　无须更改软/硬件设计。　→　拥有专利的一致性存储器服务器和动态优化技术能够提供最佳的协同验证性能。　→　支持业界主要的微处理器和控制器模型。　→　接口开放，能够集成第三方的设计和验证工具。product:Mentor Graphics Seamless Lanaguage:english Platform:Winxp/Win7 Size:1.27G

Verification of ESD structures and other protection circuits is often a time consuming and tedious task. How do you do it? Complex DRC rules? An assortment of specialized rule decks? Home-brew tools? Recently a colleague and I published a paper which used one of the Mentor tools (Calibre® PERC) to help with this ESD checking. If you’re interested, the paper is available on-line here: New Flow for Automating Verification of ESD Design Ruleshttp://www.soccentral.com/results.asp?EntryID=29425 Also of interest is the ESDA Symposium in the Los Angeles area (Anaheim to be precise) over the coming week. I’d encourage you to pop in if you can. Last year’s event was our first at the ESDA Symposium, and it was very good. Lots of great...