Mentor Graphics Precision RTL 2011a.61
Means of synthesis of high-performance FPGA-type PLD and FPGA, optimized in terms of ease of use and high quality results. Supports a multi-million-programmable systems-on-Chip (FPSoC) the last generation. Precision RTL Synthesis receive input on the project as a description in VHDL or Verilog and implements logic synthesis with the defined limits, based on built-in libraries of manufacturers. The package has a built-in static timing analysis, the ability to analyze and debug in an incremental mode, and an intuitive user interface makes it easy to manage the process of fusion as an experienced engineer, and beginner. Precision RTL Synthesis includes a unique optimization algorithm – Architecture Signature Extraction (ASE), which automatically selects the most critical in the project area, limiting the...