Cadence IUS 10.02 For Linux
This course addresses features specific to Incisive® mixed-language (VHDL, Verilog®, and SystemC®) event-driven digital simulation. The course treats these languages equivalently; students may do most labs in their choice of language. Learning Objectives Compiling, elaborating, linking, simulating, and debugging your design Optionally: * Simulating mixed-language designs * Annotating HDL design timing data * Integrating user C or C++ applications with an HDL design Agenda Day 1 1. Incisive simulation overview 2. Setting up the simulation environment 3. Compiling your design 4. Linking SystemC components 5. Elaborating your design 6. Simulating your design Day 2 1. Debugging with the textual interface 2. Debugging with the graphical interface 3. Employing simulator-related utilities If sufficient time: 1. Simulating mixed-language designs 2. Annotating SDF...