Mentor Graphics HDL Designer 2007.1a Linux
::::::English Description:::::: HDL Designer Linux delivers solutions optimizing the design creation, synthesis and verification processes of advanced ASIC and FPGA designs in a team environment. Comprehensive Design Creation & RTL Reuse Environment Any Silicon PLD, FPGA, Platform FPGA, Structured ASIC, ASIC Prototypes, ASICs and SOCs Any Vendor Actel, Altera, Atmel, ChipExpress, Lattice, Xilinx, plus any ASIC foundry Any Language VHDL, Verilog, SystemVerilog, C/C++, PSL Any Flow Integrated with all leading Simulation, Emulation & Formal solutions Integrated with all commercial synthesis and P & R environments Optimizing RTL Reuse Practical reuse (online demo) (datasheet) Optimizing The Design Process Cut design time in half: Rapid design development process Team productivity: Team design flow and version management Tune your competitive edge: Flow management...