Synopsys Formality 2008.09 SP4 AMD64
::::::English Description:::::: The Formality® Equivalence Checker uses formal techniques to prove or disprove equivalence between two versions of the same design. Equivalence checking is a type of static analysis that verifies large designs both quickly and completely without the use of test vectors. The high performance and reduced risk of static analysis has led to the rapid adoption of equivalence checking within leading verification flows, making it a must for all competitive design processes. Key Benefits共享软件资源网 Exhaustive verification, without test vectors, in a fraction of the time consumed by traditional dynamic techniques Proves functional correctness of register retiming, complex datapath, ECO, and low power implementations–from within a single product Reduces manual setup with verified automated setup guidance Verifies full-custom and...