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Artwork Mask, Modeling and User Interface Enhancements Save Time for RF Designers with Tight Deadlines and Budgets SANTA CLARA, Calif., July 31, 2008 Agilent Technologies Inc. (NYSE: A) today announced shipment of its Genesys 2008.07 release. The new Genesys release contains improvements to the reliability of artwork masks for electromagnetic (EM) verification and RF board manufacturing, along with modeling and user interface improvements. This functionality results in shorter design cycles with fewer iterations for RF designers with tight deadlines and budgets. The Genesys 2008.07 release reliably exports RF board mask and artwork files to a wider set of board fabricators, inexpensive rapid-prototyping machines and a variety of CAD/CAM software for physical product design. The release also includes a graphical artwork...

::::::English Description:::::: Mentor Graphics I/O Designer 7.3 provides bi-directional integration, data management and the ability to perform concurrent design of your FPGA and PCB. Focused on optimizing system performance, designer productivity and reducing product manufacturing costs, I/O Designer eliminates the barriers between FPGA and PCB flows and design organizations.product:Mentor Graphics IO Designer 7.3 with UPdate1 Lanaguage:english Platform:Winxp/Win7 Size:179MB

OverviewWith process geometries reaching90-nanometers (nm) and below, thereare many nanometer effects that canimpact timing. Accurate analysis ofthese effects is required to identify realtiming issues.Synopsys’ NanoTime tool is thenext-generation transistor-levelstatic timing analysis solution thataddresses the emerging challengesin signal integrity (SI) analysisassociated with custom designs.NanoTime offers concurrent timingand SI analysis, accuracy withinfive percent of HSPICE®, and theperformance required to analyzecomplex transistor circuits overnight.Its seamless integration with Synopsys’PrimeTime® product enables full-chipanalysis of designs that includes bothgate- and transistor-level blocks.NanoTime is a key component of theSynopsys custom design verificationsolution that includes CustomSim®and HSPICE for circuit simulationand ESP-CV for symbolic simulation.product:Synopsys Nanotime 2007.12 SP2 Linux Lanaguage:english Platform:Winxp/Win7 Size:81MB

IC-CAP 2008 (with Add-ons 1 & 2): Bringing Innovative Modeling Technology to Our Customers The IC-CAP 2008 release introduced the IC-CAP Target Modeling Package. Used to extract MOS models from semiconductor manufacturing process targets, the Target Modeling Package enables designers the to develop device simulation models earlier in the design cycle for faster overall integrated circuit design. The IC-CAP 2008 Add-On 1 release introduced the Hisim2.4 Model Extraction Package, an easy-to-use and efficient flow to measure and extract DC and RF parameters of the Hisim2.4.1 model. The IC-CAP 2008 Add-On 2 release introduced a similar extraction package for the Hisim_HV model for symmetrical HVMOS and asymmetrical LDMOS devices. New with this Release * Target Modeling Package * HiSIM2.4 Model Extraction...

Synplicity’s Synplify Premier Linux software is the ultimate FPGA timing closure and debug solution. It builds upon Synplicity’s industry-leading synthesis technology by adding graph-based physical synthesis and real-time simulator-like visibility into operating FPGA devices. The Synplify Premier tool’s graph-based physical synthesis technology addresses timing closure by merging optimization, placement, routing and generates a fully placed and physically optimized design ready for final routing using the FPGA vendor routing tool. The highly accurate correlation between the Synplify Premier product’s timing estimates and final design timing enables more aggressive optimization resulting in improved device performance. In addition, the Synplify Premier product offers FPGA Designers and ASIC Prototypers the most efficient method of in-system verification of FPGAs. The Synplify Premier software dramatically accelerates...

attice Announces ispLEVER 7.1 Service Pack 1 FPGA Design Tool Suite Tool Suite Includes New 3rd Party Synthesis and Simulator Versions, Integrated ORCAstra Utility and Concurrent LatticeMico32 Release HILLSBORO, OR – SEPTEMBER 8, 2008 – Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of Service Pack 1 for Version 7.1 of its ispLEVER® FPGA Design Tool Suite. The release integrates Lattice\’s ORCAstra configuration design utility, features Reveal™ Logic Analyzer support on the Linux Operating System, adds new versions of Synopsys\’ Synplify® Pro synthesis and Aldec\’s Active-HDL™ Lattice Edition simulator, includes support for automotive temperature grade LatticeXP2™ FPGAs and provides the latest LatticeMico32™ embedded open source microprocessor enhancements. \”This ispLEVER service pack adds a wide range of new utilities...

PADS®, Mentor Graphics’ world-leading desktop PCB design tool, enables you to develop PCBs within a highly productive, scalable, and easy-to-use environment. PADS solutions cover the spectrum of PCB development, from schematic entry to manufacturing preparation. But, unlike other products, we’re not ‘one-size-fits-all.’ With PADS you buy what you need. PADS Suites, available in three configurations, are our newest solutions, tailored to meet the design needs of each individual.product:Mentor Graphics PADS 2007.3 with update2 Lanaguage:english Platform:Winxp/Win7 Size:565MB

FPGA Advantage is a complete Integrated Design Environment (IDE) targeting high-complexity FPGA device design. The FPGA Advantage IDE spans the RTL FPGA design flow featuring advanced design entry, verification, synthesis and implementation sub-flows. FPGA Advantage accelerates total product design with integration of FPGA IO design as well as bi-directional integration of the PCB design flow. FPGA Advantage provides an integrated HDL flow for designing your FPGAs. FPGA Advantage enables design creation, simulation with debug and analysis, synthesis, management and documentation as a smooth flowing operation from one step to the next. Each component of FPGA Advantage is a proven point tool, but the power comes from integrating these tools tightly together to create a unique HDL design methodology environment for...

Incisive Desktop Manager  Automated verification management Incisive Desktop Manager automates and guides the everyday deployment and visualization of verification tasks and results, increasing engineering productivity and reducing time to market.Cadence® Incisive® Desktop Manager accelerates verification plan execution by automating time-consuming manual tasks at block, chip, system, and project levels. It manages the everyday deployment of common verification tasks, together with visualization of the results. Incisive Desktop Manager also supports a coverage-based verification and debug methodology that increases coverage using incrementally-developed verification plans. Features/Benefits Speeds time to results by automating verification tasks Increases engineering productivity by managing regression tests and failures Enables visualization of coverage results product:Cadence Incisive Desktop Manager (EMGR20) 2.0 Linux Lanaguage:english Platform:Winxp/Win7 Size:397MB

MoldWorks 2008 SP1 includes RTI catalogue and support for Vista Product:MoldWorks2008 SP1.0 for SolidWorks Win32 Lanaguage:english Platform:Winxp/Win7 Size:134MB