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With the SPB16.3 release of AMS Simulator, several new cursor enhancements are available: * Setting cursor width and color * Placing cursors across multiple traces and plots * Exporting and copying cursor data * Dockable cursor window Read below to see these new features.Placing cursors across multiple traces and plots You can add cursors across multiple traces and plots. The cursor window displays values for the different traces. To apply the cursors to a different trace 1. Click in the cursor box to freeze the cursor locations on the current trace.2. After freezing the cursor locations, right-click on the new trace you want to apply the cursors. – or – 1. From the Trace menu, choose Cursor, then choose Freeze...

Circuit designSelectively automating non-critical aspects of custom IC design allows engineers to focus on precision-crafting their designs. Cadence® circuit design solutions enable fast and accurate entry of design concepts—which includes managing design intent in a way that flows naturally in the schematic—coupled with an advanced design environment that allows designers to visualize and understand the many interdependencies of an analog, RF, or mixed-signal design and their effects on circuit performance.Features/Benefits * Speeds common design entry tasks by 5x (GXL) * Enables adding design constraints to the schematic to maintain consistency and preserve the designer’s intent on critical pieces of the design * Eases the development of multiple tests over multiple conditions to validate a design’s performance against the target specification...

Cadence SPECCTRA for OrCADFor robust PCB interconnect routingCadence® SPECCTRA® for OrCAD® solves the challenges of complex interconnect routing withpowerful, automated technology. This robust, production-proven autorouter includes a batch routingmode with extensive user-defined routing strategy control as well as built-in automatic strategycapability. SPECCTRA for OrCAD achieves faster, more efficient routing using algorithms that lookat the design and draw from a library of proven strategies based on the design’s content. It thenconfigures and executes the router as required.An interactive routing environment, SPECCTRA for OrCAD features realtime interactive tracepushing and shoving aids to make quick manual edits to traces. An interactive placementenvironment with extensive floorplanning functionality and complete component placementfeatures eliminates the need to switch applications to make placement changes to optimize routing.By...

Cadence Encounter RTL Compiler 9.1 Linux allows engineers to look across the entire design as they employ concurrent optimization techniques, such as making tradeoffs among timing, area, and power. To maximize performance, decrease die size, reduce power consumption, and boost productivity, designers need a global synthesis solution that enables concurrent optimization of timing, area, and power. Encounter RTL Compiler, a key component of the Cadence Logic Design Team Solution, delivers production-proven global synthesis for faster, smaller, and low-power chips in less time. With its unique set of patented global-focus algorithms, combined with new physically-aware optimization and analysis, Encounter RTL Compiler cuts design time while ensuring the highest quality of silicon. Features/Benefits A well-balanced logic structure isolates critical paths and reduces power,...

Cadence Assura 4.10 Linux Physical Verification supports both interactive and batch operation modes with a single set of design rules. It uses hierarchical processing and multi-processing for fast, efficient identification and correction of design rule errors. Unique pattern-checking capabilities enable simple rule development and maintenance for hard-to-write rules. Assura Physical Verification incorporates advanced sub-65nm process parameter measurement, nanometer design rules for DFM, and process design rule checks. Assura Physical Verification reduces overall verification time because it incorporates a fast and intuitive debug capability integrated within the Virtuoso® custom design environment. It facilitates schematic-to-layout cross-probing and incorporates technologies that fix, extract, and compare errors. An interactive short locator accelerates recognition and fixing of shorts. Assura Physical Verification also offers plug-and-play integration...

Cadence  Incisive  Formal Verifier(IFV) allows design teams to start RTL block verification months earlier than when using traditional simulation-based techniques. Its formal, assertion-based approach and exhaustive analysis capabilities ensure verification quality by pinpointing the source of bugs and detecting the corner-case errors that other methods often miss. Incisive Formal Verifier integrates easily into established design and assertion-based verification flows through its support of industry-standard languages. Features/Benefits Speeds time to block design closure with early error detection, analysis, and debug Reduces risk of re-spin by finding bugs that other verification approaches miss Eases chip-level verification by delivering higher block-level verification quality Leverages the same assertions as Incisive simulation, acceleration, and emulation technologies Supports all industry-standard assertion formats, including SystemVerilog Assertions (SVA),...

Today\’s SPB 16.2 release is significant for the Cadence Allegro and OrCAD families of products, but more importantly, I think it brings a lot of new functionality for PCB designers. I will be talking about the improvements in this release over a few blog posts in coming days and weeks. First and foremost, we have added a Constraint Driven PCB Design Flow for build-up designs to accelerate miniaturization. As you know, customers in high-end consumer electronics market place, mobile phone makers, GPS navigation system makers have been dealing with miniaturization for quite some time now and have been using build-up process to fabricate PCBs. With smaller and smaller pin pitch BGAs being introduced — with 0.8 mm pin pitch or...

With the Cadence® SoC Encounter™ RTL-to-GDSII System, engineers can account for the effects of interconnect across the entire chip—from the outset of the implementation cycle. It combines RTL synthesis, silicon virtual prototyping, automated floorplan synthesis, clock network synthesis, design for manufacturability and yield, low-power and mixed-signal design support, and nanometer routing. It also offers the latest capabilities to support advanced 65nm and 45nm designs. Features/Benefits * Supports multiple implementation styles with built-in power-planning, floorplanning, and signal integrity analysis * Supports multiple methodologies for flip-chip implementation, promoting concurrent chip/package design * Provides a statistical static timing analysis solution and standardized ECSM library models * Incorporates cutting-edge yield and low-power design capabilities * Handles 50M+ gate designs at 90nm and below Encounter...

！ Optimizing designs for leakage and dynamic power helps designers reduce energy consumption and packaging costs. But these advanced low-power design methods also complicate the verification task, introducing risk during synthesis and physical implementation. Full-chip, gate-level simulation is not a practical or scalable methodology for verifying today’s large, complex designs. Cadence® Encounter® Conformal® Low Power enables designers to verify and debug multimillion-gate designs optimized for low power, without simulating test vectors. It combines low-power structural and functional checks with world-class equivalence checking to provide superior performance, capacity, and ease of use. Features/Benefits Minimizes silicon re-spin risk by providing complete verification coverage Detects low-power implementation errors early in the design cycle Verifies multimillion-gate designs much faster than traditional gate-level simulation Closes...

Encounter Timing System Accelerate design closure and signoff with a single view of timingEncounter Timing System serves both front-end logic designers looking for high-quality, high-throughput timing analysis and ease of use, as well as back-end implementation engineers requiring electrical analysis and a common timing engine for silicon-accurate signoff. With Cadence® Encounter® Timing System, designers benefit from a consistent, integrated, multi-CPU enabled, static timing analysis (STA) environment for place-and-route optimization and signoff verification, leading to faster design closure and better flow convergence. Encounter Timing System helps designers analyze and debug multimillion-gate designs with significant gains in productivity. Global timing debug pinpoints the root cause of timing and constraint issues at the push of a button. Sophisticated delay calculation ensures accuracy and...