Cadence ASI v16.60.004 Win32&Win64
In this course, you use the Allegro® Sigrity™ SI software to develop design rules for high-speed designs. You add the resulting physical and electrical constraints to the design through topology templates. These constraints drive the routing of nets on the printed circuit board. You run preroute and postroute signal simulations to analyze the PCB for reflection, crosstalk, and other high-speed design factorsLearning Objectives After completing this course, you will be able to:o Create, extract, and explore topologieso Run solution space analysiso Create an electrical constraint seto Apply constraints to drive placement and routingo Run postroute DRC checko Use template revision to update the ECSet applied to the netso Analyze nets on the routed board design for signal integrityo Create a...