EDA Design Page 78

Cadence INCISIVE v15.20.001 Key Benefits Fuels testbench automation, analysis, and reuse for increased productivity Ensures verification quality by tracking industry-standard coverage metrics Drives and guides verification with an automatically back-annotated and executable verification plan Whether you and your team are challenged by countless runs to meet closure and coverage goals, interactive efforts to validate power domain and reset verification intent, or finding and debugging long deep deadlocks, Incisive® Enterprise Simulator improves turnaround time and throughput. With process automation technology, native high-performance engines, power analysis, and advanced debug capabilities, you can verify the most complex chips and systems. Incisive Enterprise Simulator supports all IEEE-standard languages and methodologies as well as power formats and provides a comprehensive plan-to-closure methodology, improving productivity, project...

Crosslight APSYS 2018 APSYS, Advanced Physical Models of Semiconductor Devices, is based on 2D/3D finite element analysis of electrical, optical and thermal properties of compound semiconductor devices, with silicon as a special case. Emphasis has been placed on band structure engineering and quantum mechanical effects. Inclusion of various optical modules also makes this simulation package attractive for applications involving photosensitive or light emitting devices. Applications Diodes, transistors and various other types of silicon devices LEDs and OLEDs Solar cells Photodetectors (PD) High electron mobility transistors (HEMT) Heterojunction bipolar transistors (HBT) Resonant tunneling diodes (RTD) Quantum well infrared photodetectors (QWIP) Small MOS devices with strong quantum mechanical effects (Quantum-MOS) Power devices Features Restart from previous saved status Industry leading numerical convergence...

Cadence Allegro and OrCAD 17.20.030 UpdateCadence Design Systems, Inc. has released update of OrCAD Capture, PSpice Designer and PCB Designer 17.2-2016. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices. Cadence OrCAD, Allegro, and Sigrity technologies and solutions provide unique, cost-effective, and scalable capabilities for designing some of the electronics industry\’s market-leading products. With industry-proven OrCAD solutions, you get affordable yet sophisticated PCB technology, right from your desktop. Allegro PCB design solutions enable a constraint-driven design flow, from concept to manufacturing. Unique Sigrity technology provides the only proven path for system-level, power-aware signal integrity (SI)/simultaneous switching noise (SSN) compliance.product:Cadence Allegro and OrCAD 17.20.030 Update Lanaguage:english Platform:Win7/WIN8 Size:1DVD

Remcom Wireless InSite 3.2.0.3Wireless InSite Features Wireless InSite\’s unique collection of features simplifies the analysis of even the most complex and massive propagation problems.X3D Propagation Model X3D is a 3D propagation model with no restrictions on geometry shape or transmitter/receiver height. This accurate model includes reflections, transmissions and diffractions along with atmospheric absorption. Supports frequencies up to 100 GHz. Diffuse Scattering Capture effects of scattering on complex impulse response and cross-polarized received power for mmWave applications. MIMO Simulations The X3D model provides a unique ray tracing capability for simulating MIMO antennas for 5G, WiFi and other applications. Wireless InSite MIMO simulates the detailed multipath of large numbers of MIMO channels while overcoming the increased level of computations required for traditional...

Mentor Graphics FloEFD 17.0content of suite: 1. FloEFD.17.0.v3969.Stabdalone.Win64 (no external CAD is needed) 2. FloEFD.17.0.v3969.CatiaV5.Win64CATIA V5 R19 (recommended SP9)CATIA V5 R20 (recommended SP7)CATIA V5 R21 (recommended SP6)CATIA V5-6 2012 (R22) (recommended SP6)CATIA V5-6 2013 (R23) (recommended SP6)CATIA V5-6 2014 (R24) (recommended SP7)CATIA V5-6 2015 (R25) (recommended SP6)CATIA V5-6 2016 (R26) (recommended SP4)CATIA V5-6 2017 (R27) – NOT SUPPORTED! 3. FloEFD.17.0.v3969.Creo.Win64Pro/ENGINEER Wildfire 4 (recommended datecode M220)Pro/ENGINEER Wildfire 5 (recommended datecode M280)Creo Parametric v1.0 (recommended datecode M050)Creo Parametric v2.0 (recommended datecode M240)Сreo Parametric v3.0 (recommended datecode M120)Creo Parametric v4.0 – NOT SUPPORTED! 4. FloEFD.17.0.v3969.NX.Win64Siemens NX 7.5.0 – 7.5.5 (MP10)Siemens NX 8.5.1 – 8.5.2Siemens NX 8.0.0 – 8.0.3Siemens NX 9.0.1 – 9.0.3Siemens NX 10.0.0 – 10.0.3Siemens NX 11.0.0 – 11.0.2Siemens NX 12.0 –...

Mentor Graphics Catapult HLS v10.1b for linuxThe Catapult High-Level Synthesis (HLS) Platform empowers designers to use industry-standard ANSI C++ and SystemC to describe functional intent and move up to a more productive abstraction level.Catapult High-Level Synthesis The Catapult High-Level Synthesis Platform empowers designers to use industry-standard ANSI C++ and SystemC to describe functional intent and move up to a more productive abstraction level. From these high-level descriptions, Catapult generates production-quality RTL. By speeding time to RTL and by automating the generation of bug free RTL, Catapult significantly reduces the time to verified RTL. The Catapult Platform pairs synthesis with the power of formal C property checking to find bugs early at the C/C++/SystemC level and to comprehensively verify source code...

Mentor.Graphics.Questasim.v10.6c for linuxQuesta’s core simulation and debug engine The Questa® Advanced Simulator combines high performance and capacity simulation with unified advanced debug and functional coverage capabilities for the most complete native support of Verilog, SystemVerilog, VHDL, SystemC, SVA, UPF and UVM. The Questa Advanced Simulator is the core simulation and debug engine of the Questa Verification Solution; the comprehensive advanced verification platform capable of reducing the risk of validating complex FPGA and SoC designs. Questa spans the levels of abstraction required for complex SoC and FPGA design and verification from TLM (Transaction Level Modeling) through RTL, gates, and transistors and has superior support of multiple verification methodologies including Assertion Based Verification (ABV), the Open Verification Methodology (OVM) and the Universal...

Mentor Graphics Precision Synthesis 2017.1 Linux64 Precision Synthesis offers high quality of results, industry-unique features, and integration across Mentor Graphics’ FPGA Flow– the industry’s most comprehensive FPGA vendor independent solution.FPGA Synthesis Product SuitePrecision RTL Plus Offers breakthrough advantages for both commercial applications and for mil-aero and safety-critical systems. Features include multi-vendor physical synthesis, incremental flows, low power synthesis, and… View Product OverviewPrecision RTL Plus + LeonardoSpectrum A single product to access both Precision RTL Plus and LeonardoSpectrum, Precision RTL Plus + Leo Station is an ideal upgrade for existing LeonardoSpectrum users. View Product OverviewPrecision Hi-Rel Offers synthesis-based radiation effects mitigation for safety-critical and high reliability applications.LeonardoSpectrum Offers a well-proven, mature synthesis solution for both FPGAs and ASICs. Precision RTL Offers...

Aldec Riviera-PRO 2017.02 Functional Verification Riviera-PRO™ addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.Verification-Platform-GrowsTop Features and Benefits High Performance Simulation Extensive simulation optimization algorithms to achieve the highest performance in VHDL, Verilog/SystemVerilog, SystemC, and mixed-language simulations The industry-leading capacity and simulation performance enable high regression throughput for developing the most complex systems Support for the latest Verification Libraries, including Universal Verification Methodology (UVM) Advanced Debugging Integrated multi-language debug environment enables automating time-consuming design analysis tasks and fixing bugs quickly UVM Toolbox, UVM graph,...

Valor Genesis 2000 V10.5 Features Automating workflows from customer design to the production floor Genesis 2000® creates a seamless pre-production environment for automating processes, from the customer’s door to the production floor. Genesis 2000® combines planning, product engineering, and tooling into a single seat, supported by a unified ODB++ database. Add modular integration and an intuitive interface and you have unmatched bottom line results: higher throughput and measurable cost savings. Automation for speed and accuracy With the most extensive line-mode command access in the industry and embedded automation tools, you can automate planning, job analysis, editing, photo-tool creation, drill, rout, fixturing, AOI, electrical testing outputs, and workflow management. The accuracy of ODB++ contour-based algorithms means high repeatability, improved quality, and...