EDA Design Page 74

JMAG Designer 17.1 Solver Solver speed is directly related to model accuracy and reliability. Finite element analysis comes down to solving very large matrices. JSOL has developed advanced techniques to solve these matrices faster and produce more consistent results.JMAG users have some of the most advanced solver algorithms at their fingertips, and can be certain that JSOL will continue to adopt the latest calculation architecture within JMAG.Parallel Computing High speed processing and scalability are the two main goals of parallel processing.JMAG supports both shared and distributed memory processing and can incorporate the graphics processing unit (GPU) into calculations.From the desktop to clusters and cloud computing, JMAG’s parallelization technologies can be used in a wide range of environments. Utilizing these architectures...

Infolytica ThermNet 7.8ThermNet simulates the steady-state and transient temperature distribution of specified heat sources. Coupling with MagNet and ElecNet provides accurate electro-thermal analysis for devices such as electric machines (motors and generators), transformers, induction heating, surge arrestors and dielectric heating.–Simulates the temperature distributions caused by specified heat sources in the presence of thermally conducting materials–Coupling with MagNet for heating effects due to eddy current and hysteresis losses in the magnetic system–Coupling with ElecNet for heating effects due to electric lossesProduct:Infolytica ThermNet 7.8 Lanaguage:english Platform:Win7/WIN8 Size:1CD

Infolytica MotorSolve 6.1.0.9 x64Motor designers can rapidly simulate and get machine performance characteristics using MotorSolve, the powerful software that offers their complete analysis needs in one design environment.The template-based interface combined with the variational geometry modeling makes the software easy to use yet flexible enough to handle virtually any motor design. Rotor and stator geometries can also be directly imported. MotorSolve user interface version 5MotorSolve simulates machine performance using an automated finite element analysis engine. There is no need to construct the model, perform mesh refinements and extensive post-processing to extract motor related results. MotorSolve performs these operations for the user.Need to do a quick initial design check? Validating your final spec? Or somewhere in between? Choose from several analysis...

Coventor SEMulator3D 7.0Coventor SEMulator3D 7.0 – the newest version of its semiconductor virtual fabrication platform. With added features, performance improvements, and a new Device Analysis capability, SEMulator3D 7.0 addresses both process and device simulation while lowering the barriers to advanced semiconductor technology development. The new Device Analysis capability enables seamless understanding of how process changes, process variability, and integration schemes directly impact transistor device performance. SEMulator3D Device Analysis The new Device Analysis capability can extract electrical characteristics of a transistor and explore process variability on device operation, all directly within SEMulator3D. Designers can generate transistor IV curves and perform automatic device parameter extraction from those curves. Transistor performance can be measured across changes in patterning, lithography, etch, deposition, and other...

Cadence Spectre 17.10 LinuxCadence Spectre Circuit Simulator provides fast, accurate SPICE-level simulation for analog, radio frequency (RF), and mixed-signal circuits. It is tightly integrated with the Cadence Virtuoso® custom design platform and provides detailed transistor-level analysis in multiple domains. Its superior architecture allows for low memory consumption and high-capacity analysis. Features– Provides high-performance, high-capacity SPICE-level analog and RF simulation out of the box for accuracy and convergence– Enable the tradeoff between accuracy and performance through user-friendly simulation setup applicable to the most complex analog and custom-digital ICs– Uses the +postlayout option to provide efficient post-layout simulation with RLCK parasitics– Utilizes efficient multi-threaded technology to improve simulation throughput– Simulates distributed components modeled using S-parameter models (n-port) and lossy coupled transmission line...

Cadence MDV 18.03Metric-Driven Signoff is a unique Cadence methodology and technology for measuring and signing off on the design and verification metrics used during the many milestones typical in any integrated circuit (IC) development. While milestones and metrics vary by design type and end application, the final verification signoff will at, a minimum, contain the criteria and metrics within a flexible, human-readable, user-defined organizational structure. Automated data collection, project tracking, dashboards, and in-depth report techniques are mandatory elements to eliminate subjectivity, allowing engineers to spend more time on verification and less time manually collecting and organizing data.product:Cadence MDV 18.03 Lanaguage:english Platform:Linux/Macosx Size:1dvd

Cadence INCISIVECadence Design Systems, Inc., a leader in global electronic design innovation, introduced its leading functional verification platform and methodologies, INCISIVE 15.20.As electronic products across all market segments become more sophisticated, developing their underlying hardware and software, and integrating the two sides, continues to grow more complex. Early software development, hardware verification, hardware/software integration, and integrated system validation have become primary challenges, increasing development costs, project schedules, and risks.Using the Cadence Verification Suite, you can reduce system integration time by up to 50%, accelerating intellectual property (IP) development, system-on-chip (SoC) integration, and concurrent hardware/software development. This verification suite is comprised of core engines, verification fabric technologies, and solutions spanning these technologies, as shown in Figure 1.Core engines include JasperGold formal...

Mentor Graphics Tessent 10.7 The Tessent® Product Suite The Tessent product suite provides comprehensive silicon test and yield analysis solutions that address the challenges of manufacturing test, debug, and yield ramp for today’s SoCs. Built on the foundation of the best-in-class solutions for each test discipline, Tessent brings them together in a powerful test flow that ensures total chip coverage.Tessent Product AreasAutomotive The rapid growth in automotive ICs has ushered in a new era in semiconductor test. Both device suppliers and integrators are scrambling to understand and define critical quality and reliability requirements and implementation solutions. Tessent Automotive can help.Logic Test Mentor Graphics offers the industry’s most powerful suite of logic test solutions with more than two decade of successful...

Cadence.IC.Design.Virtuoso.06.17.721.Hotfix.Only.Linux 1DVDFor the builders of tomorrow, creating the electronic systems that enable smart living will require advanced design technologies on multiple levels—semiconductor, chip packaging, system interconnect, hardware-software integration, system verification, and more. Past approaches to design that address these levels disjointedly are inadequate for the increasing complexity, low-power requirements, and shorter time-to-market challenges that designers face today. Successful companies will thrive by collaborating with ecosystem leaders in electronic design automation, intellectual property, chip fabrication, and other parts of the value chain to create a comprehensive environment for System Design Enablement (SDE). Cadence® custom/analog/RF solutions are a key component of the SDE strategy. Selectively automating non-critical aspects of custom IC design allows engineers to focus on precision-crafting their designs. Cadence circuit...

Cadence Xcelium v18.03.001 Linux Key Benefits Provides an average 2X improved single-core performance Offers an average multi-core performance speed-up of 3X for RTL design simulation, 5X for GLS, and 10X for DFT simulations running on today’s servers Provides parallelism with multi-core speed-up, benefiting event-dense simulation runs of all types Further extends innovation within the Cadence Verification Suite Support expands from x86 CPUs to include Arm-based servers Cadence® Xcelium™ Parallel Logic Simulation is the EDA industry’s first production-ready third-generation simulator. It is based on innovative multi-core parallel computing technology, enabling systems-on-chip (SoCs) to get to market faster than current solutions. On average, customers can achieve 2X improved single-core performance and more than 5X improved multi-core performance versus previous generation simulators. The...