EDA Design Page 74

Synopsys Formality vO-2018.06 SP1 Formality and Formality UltraVerifies the Toughest Designs Synthesized with Design Compiler Formality® is an equivalence-checking (EC) solution that uses formal, static techniques to determine if two versions of a design are functionally equivalent. The size and complexity of today’s designs, coupled with the challenges of meeting timing, area, power and schedule, requires that the newest, most advanced synthesis optimizations be fully verifiable. Formality supports all DC Ultra and Design Compiler Graphical optimizations and so provides the highest quality of results that are fully verifiable. Formality supports verification of power-up and power-down states, multi-voltage, multi-supply and clock gated designs. Formality Ultra adds innovative matching and verification technologies to efficiently guide designers through the implementation of functional ECOs...

Accelerate Innovation withDesign Compiler Graphical “With Design Compiler Graphical, we are experiencing 10% faster timing and very tight correlation to IC Compiler…Design Compiler Graphical has also helped us reduce area and is now a standard component of our design flow.” — Mellanox TechnologiesAccelerate Design Innovation and Maximize Productivity Synopsys\’ Design Compiler family of products maximizes productivity with its complete solution for RTL synthesis and test. Design Compiler Graphical uses advanced optimizations and shared technology with IC Compiler place-and-route to deliver best-in-class quality-of-results at all process nodes. In addition, it enables RTL designers to predict, visualize and alleviate routing congestion and to perform floorplan exploration prior to physical implementation. The Design Compiler family also includes the award-winning synthesis-based test solution for...

Synopsys IC Compiler vO-2018.06 for linux IC CompilerPlace and Route System The IC Compiler™ place and route system is a single, convergent, chip-level physical implementation tool. It includes flat and hierarchical design planning, placement, clock tree synthesis, routing and optimization, manufacturability, and low-power capabilities that enable on schedule delivery of advanced designs. For Synopsys’ latest place-and-route system refer to IC Compiler II. IC Compiler is a complete place-and-route system for established and emerging process technology node designs. IC Compiler hierarchical design technology enables powerful design planning and early chip level exploration/analysis features to handle large, complex designs. IC Compiler delivers smaller die size with predictable design closure to reduce the cost of design. IC Compiler with Zroute digital router technology...

Synopsys Identify vN-2018.03 SP1 FOR WIN/LINUX Identify RTL DebuggerSimulator-like Visibility into FPGA Hardware Operation The Identify® RTL debugger allows you to instrument RTL HDL and then, still at the RT-Level, debug the implemented FPGA on live, running hardware. The Identify FPGA debug software verifies a design in hardware, similar to simulation – only much faster and with in-system stimuli. The Identify RTL debugger allows you to designate sample triggers, navigate the design graphically, and mark signals in the RTL that are to serve as probes. After synthesis, the results are viewed and annotated onto the RTL source code, the HDL Analyst® RTL View, or third party, waveform viewer. This ensures RTL-to-implementation equivalence and correct operation of the FPGA design.Key Features...

Synopsys Fpga vN-2018.03 SP1 Synplify ProLogic Synthesis for FPGA Design Synplify Pro® FPGA synthesis software is the industry standard for producing high-performance and cost-effective FPGA designs. Synplify software supports the latest VHDL and Verilog language constructs including SystemVerilog and VHDL-2008. The software also supports FPGA architectures from a variety of FPGA vendors, including Altera, Achronix, Lattice, Microsemi and Xilinx, all from a single RTL and constraint source. Synplify Pro software uses a single, easy-to-use interface and has the ability to perform incremental synthesis and intuitive HDL code analysis.product:Synopsys Fpga vN-2018.03 SP1 Lanaguage:english Platform:Win/Linux Size:1DVD

Autodesk EAGLE Premium v9.1.2 PCB design made easy Make anything with EAGLE PCB design software. Professional power for every electronics designer. Powerful, easy-to-use tools Autodesk EAGLE is an electronic design automation (EDA) software. Enabling printed circuit board (PCB) designers to seamlessly connect schematic diagrams, component placement, PCB routing, and comprehensive library content.Product:Autodesk EAGLE Premium v9.1.2 Lanaguage:english Platform:Win7/WIN8 Size:1CD

Keysight Physical Layer Test System(PLTS) 2018Key Features & Specifications Breakthrough spatial resolution of 6 picoseconds with N5291A PNA mm-wave system (900 Hz to 120 GHz) Python-based math function support for remote programming and automation 64-port S-parameter analysis for post-measurement characterization DescriptionNEW PLTS 2018 Breakthrough Spatial Resolution of 6 PicosecondsThe new Physical Layer Test System (PLTS) 2018 has significant breakthrough capabilities with regards to resolving adjacent impedance discontinuities within high-speed interconnects, such as cables, backplanes, PCBs and connectors. Many signal integrity laboratories around the world have benefited from the power of PLTS in the R&D prototype test phase. PLTS 2018 now supports the new N5291A PNA MM-wave system that provides a single continuous sweep of 900 Hz to 120 GHz in...

Mentor Graphics Calibre 2018.2.33.24 Mentor\’s IC verification and sign-off includes not only traditional rule-based physical verification and parasitic extraction, but also new capabilities and automated technologies that help improve yield by enhancing the design itself. Calibre® is the overwhelming market share leader and the industry standard for IC physical verification, due to the outstanding performance, accuracy and reliability of Calibre products. Over the last two years, Calibre nmDRC™ has reduced average DRC runtime by a factor of five, while Calibre\’s innovative Hyperscaling and MTFlex™ technologies have cut memory requirements in half. Calibre nmDRC also reduced overall cycle time with incremental DRC, which allows designers to make DRC runs in parallel. As DRC violations are reported, designers can immediately fix and...

Cobham Opera 16.0 R1Opera provides the complete toolchain for electromagnetic design, simulation and analysis of results, for use on 32- or 64-bit Windows and Linux platforms. It consists of a powerful pre-processing environment for creating design models (or importing them from CAD programs), plus a powerful finite element analysis (FEA) solver from our range. Three generic solvers are optionally available: static electromagnetic fields (the widely used ‘Tosca’ tool) – low-frequency time-varying electromagnetic fields – high frequency time-varying electromagnetic fields* – Opera can alternatively be purchased in a number of forms optimised for specific design problems: linear and rotating machinery design – superconducting magnet quenching – space charge effects from particle beams – permanent magnet magnetisation/demagnetisation – thermal and stress analysis...

Synopsys Synplify FPGA 2018Synplify Premier solution is the industry’s most productive FPGA implementation and debug environment. It includes all the features of Synplify Pro and additionally provides a comprehensive suite of tools and technologies for advanced FPGA designers as well as ASIC prototypers targeting single FPGA-based prototypes.The Synplify Premier software delivers fast turnaround time capabilities and feedback for users seeking to quickly implement the design on the board or to tune their design projects prior to final implementation. It addresses the most challenging aspects of FPGA design including timing closure and has the ability to perform graph-based physical synthesis for more accurate upfront timing prediction. It provides flows for fast logic verification and RT-Level debug. Under the hood, it contains...