EDA Design Page 22

Cadence XCELIUM 24.05 for linux Fastest Simulator to Achieve Verification Closure for IP and SoC Designs Cadence Xcelium Logic Simulator provides best-in-class core engine performance for SystemVerilog, VHDL, SystemC®, e, UVM, mixed-signal, low power, and X-propagation. It leverages a set of domain-specific apps, including mixed-signal, machine learning-based test compression, and functional safety, that enable design teams to achieve verification closure early for IP and SoC designs. Product:Cadence XCELIUM 24.05 for linux Lanaguage:english Platform:Linux/Macosx Size:1DVD

Cadence JasperGold 24.03 for linux Key Benefits Finds more bugs in less time, earlier in the design process, compared to other verification methods Machine learning-enabled Smart Proof technology for 2X faster proofs out of the box and 5X faster regressions Advanced design scalability for 2X design capacity increase and 50% memory footprint reduction Signoff-accurate formal coverage with intuitive analysis GUI Eases debug and what-if analysis Product:Cadence JasperGold 24.03 Lanaguage:english Platform:Linux/Macosx Size:1DVD

Synopsys Custom complier v2023.12  for linux Custom Compiler Product:Synopsys Custom complier v2023.12 Lanaguage:english Platform:Linux/Macosx Size:1DVD

Synopsys laker v2023.09 Laker Product:Synopsys laker v2023.09 Lanaguage:english Platform:Linux/Macosx Size:1DVD

Synopsys corebuilder v2023.09 for linux coreBuilder Product:Synopsys corebuilder v2023.09 Lanaguage:english Platform:Linux/Macosx Size:1DVD

Synopsys Testmax vV-2023.12 Synopsys TestMAX Product:Synopsys Testmax vV-2023.12 Lanaguage:english Platform:Win7/WIN10 Size:1DVD

Synopsys primetime 2022.12 for linux The Golden Signoff Solution The PrimeTime® Suite delivers fast, memory-efficient scalar and multicore computing, distributed multi-scenario analysis and ECO fixing using POCV and variation-aware modeling. Synopsys' PrimeTime static timing analysis tool provides a single, golden, trusted signoff solution for timing, signal integrity, power and variation-aware analysis. Product:Synopsys primetime 2022.12 Lanaguage:english Platform:Linux/Macosx Size:1DVD

Synopsys Starrc vV-2023.12  for linux StarRC Product:Synopsys Starrc vV-2023.12 Lanaguage:english Platform:Linux/Macosx Size:1DVD

Synopsys ESP vV2023.12 Custom Design Formal Equivalence Checking Based on Symbolic Simulation ESP is a formal equivalence checking tool commonly used for full functional verification of custom designs such as embedded memories, custom macros, standard cells and I/O cell libraries. It is used to ensure that two design representations are functionally equivalent. These designs may be represented as Verilog behavioral model, RTL, Gate, Switch or SPICE or .db netlist views. Product:Synopsys ESP vV2023.12 Lanaguage: Platform:Linux/Macosx Size:1DVD

Synopsys Hspice vu-2023.03 sp2 for linuxThe Gold Standard for Accurate Circuit Simulation As the ‘golden accuracy’ cornerstone of the PrimeSim™ solution, HSPICE®, now PrimeSim™ HSPICE® simulator, is seamlessly integrated with and empowered by other simulation engines in the continuum. PrimeSim HSPICE is the industry’s ‘gold standard’ for accurate circuit simulation and offers foundries-certified MOS device models with state-of-the-art simulation and analysis algorithms. With extensive usage in chip/package/board/backplane signal integrity simulation, cell and memory characterization, and analog mixed signal IC design, PrimeSim HSPICE is the industry’s most popular, trusted and comprehensive circuit simulator.  Product:Synopsys Hspice vu-2023.03 sp2 Lanaguage:english Platform:Linux/Macosx Size:2DVD