EDA Design Page 150

SoC GDS offers an intuitive user interface, providing advanced productivity enhancing functionalities, throughou the design creation and validation chains. SoC GDS addresses a wide range of needs, from quick and easy layout viewing, to final insertions of cells before mask generation, via advanced hierarchical integration of blocks, including solutions for preserving confidentiality in case of verifications. This framework independent Streamer focuses on standard exchange formats for bridging proprietary EDA Frameworks. Through dedicated options, SoC GDS fits the needs of Virtual Component providers, SoC integrators and process/product engineers. It is also the ideal solution t complete quality procedures for acceptance of layout databases by chip finishing teams, mask shops or silicon foundries.Product:Dolphin.Integration.SoC.GDS.v6.6.0 Lanaguage:english Platform:Winxp/Win7 Size:47 MB

SMASH is the reference Analog and Mixed-Signal (AMS), Logic and Mixed-Signal (LMS) and All-in-One Simulator enabling truthfully the combination of digital, logic and analog multi-domain modeling with no need for a cosimulation backplane, as well as Instruction Set Simulation (ISS). Moreover, the extensive support of design kits and foundry model parameter sets is regularly enhanced with new and emerging SPICE device model implementations (Level 49, from BSIM 3 to BSIM 4v6, EKV, ACM, MM9, VBIC, MEXTRAM, JUNCAP2, PSP).Product:Dolphin Integration Smash v5.15.0 Lanaguage:english Platform:Winxp/Win7 Size:132 MB

Calibre® is the overwhelming market share leader and the industry standard for IC physical verification, due to the outstanding performance, accuracy and reliability of Calibre products. Over the last two years, Calibre nmDRC™ has reduced average DRC runtime by a factor of five, while Calibre\’s innovative Hyperscaling and MTFlex™ technologies have cut memory requirements in half. Calibre nmDRC also reduced overall cycle time with incremental DRC, which allows designers to make DRC runs in parallel. As DRC violations are reported, designers can immediately fix and recheck just the affected areas, while the initial DRC run continues. To handle complex and multi-variate, multi-dimensional checks that are not adequately addressed by traditional design rules, Calibre nmDRC\’s equation-based DRC (eqDRC) capability enables designers...

FloTHERM enables engineers to create virtual models of electronic equipment, perform thermal analysis, and test design modifications quickly and easily before any physical prototypes are built. FloTHERM uses advanced CFD techniques to predict airflow, temperature, and heat transfer in components, boards, and complete systems. With a 98% user recommendation rating, FloTHERM is the undisputed world leader for electronics thermal analysis and has more users, application examples, libraries and published white papers than all otherModels that range in scale from single ICs on a PCB to full racks of electronics are assembled quickly from a complete set of SmartParts (intelligent model creation macros) that are supplied with FloTHERM from a large list of suppliers from around the globe. SmartParts capture modeling...

Want a powerful, yet easy to use simulation environment? SynaptiCAD\’s simulation and debugging tools provide a standard interface for controlling all of your simulation tools. SynaptiCAD\’s timing diagram editors have the most extensive and accurate timing analysis features available in any timing diagram editor on the market including delay correlation, reconvergent fan-out, and clocks that model jitter and buffer delays. Three different levels of editing let you pick the best price and feature set for your application. Free yourself from the time-consuming process of manually writing Verilog, VHDL, and SystemC testbenches. Generate them graphically from timing diagrams.SynaptiCAD provides 3 levels of test bench generation to meet all your design needs. SynaptiCAD offers support for the latest test equipment and emulation...

This document describes how to install the HSPICE product.Note:The installation instructions in this document are the most up-to-dateavailable at the time of production. However, changes might have occurred.For the latest installation information, see the product release notes ordocumentation.This document provides instructions for UNIX, Linux and Windows platforms.This document includes the following sections:■Media Availability and Supported Platforms■Disk Space Requirements■Installing the Software on UNIX or Linux Platforms■Configuring HSPICE and AvanWaves for UNIX and Linux■Setting Up the User Environment on UNIX and Linux■Verifying the Installation■Installing the Software on Windows PlatformsHSPICE Integration to CadenceTM Virtuoso® Analog Design Environment Related Documentation and Customer SupportImportant:You must set the DISPLAY environment variable before you install thesoftware. Because the HSPICE postinstallation script is GUI based, the toolinstallation will...

CoWare announced the 2010.1 release of CoWare SPW products. The SPW 2010.1 release advances the LTE (Long Term Evolution) Wireless Reference Library and adds a complete Xilinx implementation flow that includes direct source translation technology from C Data Flow (CDF) into RTL. The CoWare SPW 2010.1 release is available immediately. With this release, CoWare has reverted back to the product’s original SPW name (previously Signal Processing Designer, SPD). The new Xilinx flow combines SPW hardware implementation technology for RTL generation with Xilinx’s highly-optimized IP components from its ISE flow into one, easy-to-use flow. SPW 2010.1 now also offers direct source translation technology which takes CDF models and translates them to RTL. Using the polymorphism in SPW, this technology allows the...

Synplify PremierThe Synplify Premier solution is the industry\’s most productive FPGA implementation and debug environment. It includes all the features of Synplify Pro and additionally provides a comprehensive suite of tools and technologies for advanced FPGA designers as well as ASIC prototypers targeting single FPGA-based prototypes. The Synplify Premier software delivers fast turnaround time capabilities and feedback for users seeking to quickly implement the design on the board or to tune their design projects prior to final implementation. It addresses the most challenging aspects of FPGA design including timing closure and has the ability to perform graph-based physical synthesis for more accurate upfront timing prediction. It provides flows for fast logic verification and RT-Level debug. Under the hood, it contains...

CX-Supervisor is dedicated to the design and operation of PC visualisation and machine control. It is not only simple to use for small supervisory and control tasks, but it also offers a wealth of power for the design of the most sophisticated applications. CX-Supervisor boasts powerful functions for a wide range of PC based HMI requirements. Simple applications can be created rapidly with the aid of a large number of predefined functions and libraries, and even very complex applications can be generated with a powerful programming language or VBScript™. CX-Supervisor has an extremely simple, intuitive handling and high user friendliness. Importing ActiveX® components makes it possible to create flexible applications and extend functionalityThe Data Log Viewer has been completely re-written...

The VSM AdvantageThe Proteus Design Suite is wholly unique in offering the ability to co-simulate both high and low-level micro-controller code in the context of a mixed-mode SPICE circuit simulation. With this Virtual System Modelling facility, you can transform your product design cycle, reaping huge rewards in terms of reduced time to market and lower costs of development. If one person designs both the hardware and the software then that person benefits as the hardware design may be changed just as easily as the software design. In larger organisations where the two roles are seperated, the software designers can begin work as soon as the schematic is completed; there is no need for them to wait until a physical prototype...