EDA Design Page 149

X-HDL 4 is the premier Verilog VHDL bi-directional translator. X-HDL performs translation of even the most complex RTL/gate-level code efficiently and requiring few, if any, \”hand tweaks\” of the translated code. X-HDL also contains specialized algorithms which are very effective in translating behavioral-level code to functionally equivalent target-language code. Key Features •Provides both GUI and command-line modes •Performs automatic hierarchical translations as well as file-at-time translations. •Translates structural, RTL and behavioral code •Preserves comments with placement nearly identical to the source •Consistent code formatting with user customizations ◦VHDL\’87 or VHDL\’93 syntax generation ◦Verilog-2001 syntax generation ◦Code alignment controls ◦Indentation controls ◦Line wrap controls •Supports component libraries •Smart overloaded subprogram handling •Intelligently determines if translated Verilog tasks/functions are local or global...

HyperLynx® Signal Integrity enables engineers to quickly and accurately analyze and eliminate signal integrity and EMI/EMC design problems early in the design cycle. HyperLynx Signal Integrity comes ready to use in virtually any PCB design flow and offers unprecedented time-to-results, improving productivity, reducing development and product costs, and increasing product performance.Mentor Graphics Corporation (NASDAQ:MENT) today announced it was honored by the International Engineering Consortium (IEC) with the annual DesignVision award in the System Modeling and Simulation Tool category for its HyperLynx® PI (Power Integrity) product. This solution delivers fast-time-to-accurate-results in the analysis of AC and DC behavior for printed circuit board (PCB) power distribution networks. The IEC announced the winners of the DesignVision Award at DesignCon on February 2, 2010....

Genesys 2010.05 was developed based on extensive inputs from a large Genesys user community. This release of Genesys went through the most thorough quality assurance (QA) and early access (EA) customer testing compared to all previous versions of Genesys. Not only does this release address multiple reliability and performance issues, it also adds breakthrough new capabilities such as X-parameters* to both the circuit and system simulators. These along with the simplified Genesys product structure and pricing put Genesys in the best price-performance of any RF/microwave simulation tool in the industry.Genesys 2010.05 now includes: * Breakthrough nonlinear X-parameter simulation and modeling technology to enable the most accurate and convenient RF nonlinear circuit and system designs. More information about X-parameters in Microwave...

Vera language was orginally developed in Sun Micro Systems for internal ASIC verification projects. Later VERA language with VERA compiler was marketed by System Science. System Science later sold Vera to Synopsys. Synopsys released closed Vera language as openVera, which was later implemented in VCS as NTB. Currently OpenVera is support is support by @hdl Simulator, and VCS Compiler. space.gif Later Synopsys donated parts of Vera language to Verilog to give Verilog unified design and Verification feature. This new language is called SystemVerilog.product:Synopsys Vera vD-2009.12 Lanaguage:english Platform:Linux Size:287 MB

Quartus® II software version 10.0, the industry\’s #1 software in performance and productivity for CPLD, FPGA, and HardCopy ASIC designs, is now available. Download Quartus II software today! Version 10.0 supports Altera\’s new high-performance, built-for-bandwidth devices: Stratix® V GX and GS FPGAs with integrated 12.5-Gbps transceivers. Stratix V GX FPGAs are optimized for high-performance, high-bandwidth applications. Stratix V GS FPGAs target high-performance, variable-precision digital signal processing (DSP) applications with the industry-first variable-precision DSP block. Future Quartus II software releases will also support partial reconfiguration, a Stratix V FPGA feature that reduces power, cost, and board space with more effective logic planning. Version 10.0 continues to deliver Quartus II software\’s productivity advantage: 2X-3X faster compile times than the nearest competitor for...

CST proudly announces the upcoming release 2010 of its electromagnetic simulation softwareCST STUDIO SUITE™. With over 60 man years of research and development and over 3000 functional changes, CST STUDIO SUITE 2010 again sets the standard for electromagnetic simulation software.The focal points of 2010 development can be briefly summarized as implementing and integrating new solver technology, improving simulation performance and extending the applicability. The electromagnetic simulation software CST STUDIO SUITE™ is the culmination of many years of research and development into the most efficient and accurate computational solutions to electromagnetic design. It comprises CST’s tools for the design and optimization of devices operating in a wide range of frequencies – static to optical. Analyses may include thermal and mechanical effects,...

This synopsysinstaller_INSTALL_README.txt document contains installation instructions for the Synopsys Installer tool in the following sections: * General Information * Installation Procedure * Using the Installer (EST / FTP Users Only) * Post-Installation Steps * Installing From a CD * Supported Platforms and Required Operating System Patches —————————————————————–General Information—————————————————————– This document contains quick-start installation assistance for product files downloaded from Synopsys by Electronic Software Transfer (EST). For detailed installation and post-installation setup steps for most Synopsys software, see the Installation Guide. (This resource also includes CD installation assistance.) To view or obtain the Installation Guide for the current release, go to * The Synopsys Installation Guide Web page at http://www.synopsys.com/install * Synopsys Online Documentation (SOLD), which is included with the software...

Mentor Graphics PADS 9.2The PADS 9.2 Program is set to begin. You are receiving this e-mail because you have expressed an interest to participate in this beta program, or you have participated in a past program.PADS 9.2 is currently scheduled for production release in June 2010. The primary enhancements are: * Windows 7 support * Net Name Visibility * ECO Updates (maintaining trace data on ECO\’s) * Migration of user settings (customizations) on new installations * Custom thermal pads on rectangular, oval, rounded, or chamfered pads * Allow flood over of thermal relief PADS on specific instances * Layout/Router Synchronization * Differential pairs enhancements * Resizable dialog boxes in PADS Layout and Logic * PADS Logic Update from Library on...

Filed under: PCB Layout and routing, PCB design, SPB, Allegro PCB Editor, Constraint Manager, via, PCB Editor, PCB, SPB 16.3, Allegro 16.3, \”PCB design\”, SPB16.3 Current design technologies require extremely tight matching requirements right down to the overall net topologies to ensure that any deviations in propagation delays are minimized. As a result, design guidelines call for matching the number of vias for a group of signals. The prior releases of Constraint Manager support a \”MAX_VIA_COUNT\” constraint which does not meet the needs of these new design requirements. The SPB16.3 Allegro PCB Editor constraint system now supports a method to check for an equal number of vias in addition to a \”maximum\” number of vias on a group of nets...

Recommended for simulating all FPGA designs (Cyclone? Arria? and Stratix?series FPGA designs) 33 percent faster simulation performance than ModelSim?Altera?Starter edition Support for simulating small FPGA designs 10,000 executable line limitation 1) Unpack and install. 2) Copy license.dat to a permanent place. 3) Add the path+filename to your LM_LICENSE_FILE (separate other licenses with ; ) 4) Enjoy this release! Course DescriptionThis training provides an overview of Mentor Graphic\’s ModelSim® software. You will learn the basics about simulation and how to simulate with projects. You will learn how to work with multiple libraries and debug with the Dataflow window. You will view simulation waveforms in the Wave window and analyze performance with the Performance Profiler. Finally, you will analyze simulation results with...