EDA Design Page 142

Quartus® II software version 11.0, the industry\’s number one software in performance and productivity for CPLD, FPGA, and HardCopy® ASIC designs is available for download. Quartus II software version 11.0 delivers the production release of Altera’s new system-level integration tool known as Qsys. The Qsys system integration tool saves time and effort in the FPGA design process by enabling faster system development and design reuse. This version delivers expanded support for the Stratix® V FPGA family including added transceiver modes and features. Quartus II software version 11.0 also delivers faster board bring-up with improved debug solutions. These improvements include new performance monitoring capabilities in the external memory interface toolkit and improved usability with the Transceiver Toolkit. Download the Quartus II...

Xilinx introduced the ISE?Design Suite 12 software to enable breakthrough optimizations for power and cost with greater design productivity. For the first time, ISE design tools deliver \’intelligent\’ clock-gating technology that reduces dynamic power consumption by as much as 30 percent. The new suite also provides advances in timing-driven design preservation, AMBA 4 AXI4-complaint IP support for plug-and-play design, and an intuitive design flow with fourth-generation partial reconfiguration capabilities that lowers system cost for a broad range of high performance applications. With full production support for all Xilinx?Virtex?6 and Spartan?6 FPGA families, the ISE 12 release continues its evolution as the industry\’s only domain-specific design suite with interoperable design flows and tool configurations for logic, digital signal processing (DSP), embedded...

Mentor Graphics Corporation (Nasdaq: MENT) today announced the Questa™ Vanguard Program (QVP), a partnership with industry-leading companies to enhance the verification options for Questa users and build a strong and comprehensive SystemVerilog ecosystem. The Questa Vanguard Program extends Mentor Graphics breadth of verification technologies through partnerships with other industry-leading companies that provide verification related tools and methods, verification IP, conversion services, training and consulting. Through these technology alliances and strategic partnerships, Mentor Graphics leverages resources and technical expertise to deliver even greater value to Questa users, including strong product integration with other Mentor Graphics technologies (see news release \”Mentor Graphics Delivers the Next Generation of Functional Verification,\” May 8, 2006). \”Without adequate industry infrastructure, no new technologies or methodologies can...

he MDK-ARM is a complete software development environment for Cortex™-M, Cortex-R4, ARM7™ and ARM9™ processor-based devices. MDK-ARM is specifically designed for microcontroller applications, it is easy to learn and use, yet powerful enough for the most demanding embedded applications.Download MDK-LiteFeatures Complete support for Cortex-M, Cortex-R4, ARM7, and ARM9 devices Industry-leading ARM C/C++ Compilation Toolchain µVision4 IDE, debugger, and simulation environment Keil RTX deterministic, small footprint real-time operating system (with source code) TCP/IP Networking Suite offers multiple protocols and various applications USB Device and USB Host stacks are provided with standard driver classes ULINKpro enables on-the-fly analysis of running applications and records every executed Cortex-M instruction Complete Code Coverage information about your program\’s execution Execution Profiler and Performance Analyzer enable program...

Cadence® Assura® Design Rule Checker (DRC) is part of the design verification suite of tools within the Virtuoso® custom design platform. Assura DRC is a full-featured tool that supports both interactive and batch operation modes and utilizes hierar- chical processing for fast, efficient identification and correction of design rule errors in even the most advanced designs.the virtuoso customdesign platform When design objectives dictate manipulat-ing precise analog quantities—voltages,currents, charges, and continuous ratiosof parameter values such as resistance andcapacitance—companies turn to customdesign. Full-custom design maximizesperformance while minimizing area andpower. However, it requires significanthandcrafting by a select set of engineerswith very high skill levels. In addition,custom analog circuits are more sensitiveto physical effects, which are exacerbatedat new, nanometer process nodes. The Virtuoso custom...

Verification is the most time consuming task in ASIC design today.Certify ASIC RTL prototyping software from the Synopsys® Synplicity®Business Group helps accelerate the verification phase by allowing youto build multi-FPGA based prototypes of your ASIC design in an easy,intuitive fashion, and with no modifications to the original design. ASICprototypes typically deliver speeds between 10 – 80 MHz, far in excessof any other verification technology and at a lower cost than any otherhardware solution. Previous FPGA prototyping techniques have beendifficult, cumbersome, and time consuming. The Certify solutionsimplifies the prototyping process by providing an intuitive, user-friendlytool that works directly from your RTL code combined with theleading Quality of Results (QoR) that the Synplicity Business Group isknown for. Certify Highlights • Combines best-in-class...

Circuit designSelectively automating non-critical aspects of custom IC design allows engineers to focus on precision-crafting their designs. Cadence® circuit design solutions enable fast and accurate entry of design concepts—which includes managing design intent in a way that flows naturally in the schematic—coupled with an advanced design environment that allows designers to visualize and understand the many interdependencies of an analog, RF, or mixed-signal design and their effects on circuit performance. Virtuoso Schematic EditorProvides a complete design and constraint composition environment for front-to-back analog, custom-digital, RF, and mixed-signal designs.Designed to help users create manufacturing-robust designs, Cadence® Virtuoso® Analog Design Environment is the advanced design and simulation environment for the Virtuoso platform. It gives designers access to a new parasitic estimation and...

Encounter Digital Implementation System is an integrated solution that provides the fastest deterministic path to silicon realization. By leveraging and preserving design intent, enabling higher levels of abstraction, and ensuring quick convergence, it optimizes the implementation of giga-gate–scale, low-power, mixed-signal, and advanced node designs. In a single environment, Encounter Digital Implementation System supports RTL synthesis, rapid design exploration, accurate chip feasibility analysis, full-chip virtual prototyping, full-chip digital implementation, and in-design signoff. With an early, precise view of design feasibility, engineers can progress immediately to full-scale implementation and final signoff for large-scale, complex designs—without ever leaving the solution environment. BenefitsPredictability and convergence * Combines the power of RTL synthesis, early design exploration, full-chip prototyping and design implementation, in-design DFM, and final...

Laker custom IC design solutions offer the power of controllable automation and unmatched interoperability to achieve superior layout results with less effort for analog, mixed-signal, and custom digital designs. More than 300 companies, including many of the world’s leading semiconductor companies, have adopted the Laker layout system for designs down to 28 nanometers. For more information about Laker products,SpringSoft, Inc., a global supplier of specialized IC design software, is pleased to announce that its Laker™ Custom Automation Layout System has received the Best Electronic Design 2010 Award from Electronic Design Magazine. The award recognizes the advancements in custom chip digital place-and-route solutions and OpenAccess (OA) interoperability enabled by the latest release of the Laker system.Product:Laker 2010 11 p1 Lanaguage: Platform:Linux...

Ultimate Productivity for FPGA Logic Design The ISE® Design Suite: Logic Edition includes exclusive tools and technologies to help achieve optimal design results. These include Intelligent Clock-Gating for dynamic power reduction, Team Design for multi-site design teams, Design Preservation for timing repeatability, and Partial Reconfiguration for greater system flexibility, size, power and cost reduction.Achieve Greater Designer Productivity From product installation through design verification, ISE Design Suite 13 helps you make maximum use of your time and design resources. The ISE Design Suite – Logic Edition provides a complete design environment for your RTL-based design needs – with exclusive technologies such as ChipScope™ Pro and the ChipScope Pro Serial I/O Toolkit, ISE™ Simulator, and PlanAhead™ – along with Multi-processor support allowing...