ynopsys, Inc. is the solutions leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/ . NOTE: Synopsys is a registered trademark and Magellan is a trademark of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their...
The installation instructions in this document are the most up-to-dateavailable at the time of production. However, changes might have occurred.For the latest installation information, see the product release notes ordocumentation.This document provides instructions for the UNIX, Linux, and Windowsplatforms. The document includes the following sections:Preparing for InstallationInstalling SpiceExplorer and WaveView Analyzer (UNIX and Windows)Invoking SpiceExplorer and WaveView Analyzer on WindowsInstalling the SX-CDS Link PackageInstalling the SX-DAIC Link PackageInstalling the SX-VSDE Link PackageViewing and Printing SpiceExplorer and WaveView AnalyzerDocumentation in Portable Document Format (PDF)Troubleshooting SpiceExplorer and WaveView Analyzer Installation onSolaris PlatformsUninstalling SpiceExplorer and WaveView AnalyzerCustomer Supportproduct:Synopsys SpiceExplorer 2008.03 SP1 Linux Lanaguage:english Platform:Winxp/Win7 Size:54MB
Synopsys Analysis and Debug products provide a unique approach to transistor-level verification that enables engineers to efficiently analyze and debug complex AMS systems-on-chips (SoCs). CustomExplorer addresses the need for an effective transistor-level debugging environment. The tools provide a netlist-driven debugging and visualization modules, and Custom WaveView with ACE scripting option completes the package. The environment provides front-to-back productivity solutions to speedup verification cycle and reduces total design cost.product:Synopsys SpiceExplorer 2008.09 Win Lanaguage:english Platform:Winxp/Win7 Size:9MB
Paradigm™ (www.pdgm.com), a leading provider of enterprise software solutions to the global oil and natural gas exploration and production (E&P) industry, announced today the worldwide release of Paradigm SKUA™ 2008 at the European Association of Geoscientists and Engineers (EAGE) 70th Annual Conference and Exhibition in Rome, Italy. The next-generation software environment allows novice-to-advanced geoscience users to easily produce highly accurate and realistic models of the subsurface in record time through the use of a proprietary 3D methodology. The new Paradigm SKUA 2008 is a 3D modeling software environment that bridges the gap between seismic and simulation by removing current modeling limitations. The software platform leverages the innovative SKUA™ (Subsurface Knowledge Unified Approach) methodology. Its unified approach produces superior modeling results...
he industry\’s first development tool to automatically generate Triple Module Redundancy (TMR) for re-programmable FPGAs. The Xilinx Triple Module Redundancy (XTMR) technology was developed to address the special needs of FPGAs in high-radiation environments. Originally designed for space applications and proven through numerous mission-critical projects, XTMR provides full SEU and SET immunity for any high reliability Virtex®-4 FPGA design.Device Family Support * Virtex-4 * Virtex-II * Virtex System Requirement * Windows 2000/XP Software Requirements * ISE® Foundation™ Software Key Features * Automatically builds XTMR into Xilinx FPGA designs, providing complete SEU and SET immunity * Supports all design entry methods, HDLs, and synthesis tools * Provides optional SRL16 extraction capability * Allows easy integration of custom-built TMR modules * Gives...
Synopsys\’ Leda® is a programmable design and coding guideline checker that delivers full chip mixed-language (Verilog and VHDL) and mixed representation (RTL & gate) capabilities to speed development of complex system-on-chip (SoC) designs. Leda’s pre-packaged rules greatly enhance a designer\’s ability to check HDL code for synthesizability, simulatability, testability, reusability, and RTL/gate signoff. Leda detects clock synchronization-related bugs, isolates hard-to-time circuits, verifies layout considerations and improves DFT for higher ATPG coverage. Leda comes prepackaged with rules to improve performance of Synopsys tools, such as VCS MX, DC and Formality. Key Benefits * Finds complex bugs, such as those associated with multiple clock domains using static analysis * Verifies consistency of design and SDC constraints for DC, PrimeTime and Astro *...
Stimcade® is a registered trademark used for Computer Software For Use In Oilfield Well Stimulation, Namely, For Selecting Wells Which Are Candidates For Stimulation, Designing Treatments, Executing Treatments, and Evaluating Real-Time and Post-Treatment Results and owned by Schlumberger Technology Corporation. Full trade mark registration details, registered images and more information below.Product:Schlumberger StimCADE 2.0 Lanaguage:english Platform:Winxp/Win7 Size:15MB
JMAG-Studio is an electromagnetic field analysis software package developed by JRI Solutions, Ltd. thatsupports the design and development of motors, actuators, circuit components, antennas and other electricand electronic products. It has been supported and used by many companies and universities since 1983.JMAG has a long track record of use for analyzing motors and other rotating devices.JRI Solutions is constantly improving JMAG-Studio by incorporating features suggested in from our usersand by using the latest technology developed through our research and accumulated analysis expertise.Product:JMAG Studio 9.0 Lanaguage:english Platform:Winxp/Win7 Size:144MB
ICX / TAU ICX® and ICX Pro provide an intuitive user interface for engineers to explore signal integrity solutions in their high-speed designs. Engineers learning signal integrity are offered a concise view of how things work, while those more seasoned are able to investigate signal integrity effects in their designs in great detail. Components are modeled using industry standard IBIS models, with support for virtually all IC model types, while simulations are provided by our proven ICX simulation technology. With a library of default IBIS models provided, engineers can begin evaluating high-speed design solutions easily and quickly. The Tau® board-level symbolic timing analysis tool performs comprehensive worst-case timing analysis and verification on designs using an advanced symbolic timing methodology, eliminating...
Mentor Graphics日前推出I/O Designer设计工具，据称可以同时进行FPGA和板卡设计。通过I/O Designer，设计人员可以在印刷电路板设计图上分配FPGA针脚信号，当然这需要在FPGA供应商的规则限制下完成。 图形化针脚信号分配可能听起来象一项简单的任务，但其影响非常深远。Mentor表示，在实际产品研究中，使用I/O Designer后优化了电脑主板设计，使路由路线长度减少了超过15%，这将减少设计时间和制造费用。 Mentor公司系统设计部产品开发主管John Isaac表示，“在过去，FPGA设计人员独立完成FPGA设计，然后把设计发给pcb设计师，后者在FPGA针脚信号的选择方面没有主动权。当你对pcb布线时，很有可能要使用更多层和超长的连接线。” 板卡设计师通常没有机会了解FPGA设计规则，获得FPGA各针脚用处的信息。Isaac说，如果一名电脑主板设计师擅自交换了FPGA针脚，结果将会是灾难性的。 但是，I/O Designer自动设计工具可以让主板设计师根据FPGA供应商的约束和规则自主分配针脚。Isaac表示，“pcb设计师可以根据主板情况优化针脚设计，只需要这些设计不超过FPGA器件库的要求。当完成设计后，这些信息会自动发回给FPGA设计系统。”而完成所有这一切，只需要在种图形环境下“拖拉”图标实现。 除图形化分配针脚之外，I/O Designer还可以用FPGA描述自动产生示意图。 product:Mentor Graphics I/O Designer 7.4 Lanaguage:English Platform:/win2000/winxp Size:109MB